llvm-6502/test/MC/Disassembler/X86/x86-64.txt
Benjamin Kramer 1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 19:05:25 +00:00

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
# Coverage
# CHECK: vcmptrue_usps
0xc5 0x04 0xc2 0xc7 0x1f
# CHECK: vcmptrue_uspd
0xc5 0x05 0xc2 0xc7 0x1f
# CHECK: vcmptrue_usss
0xc5 0x06 0xc2 0xc7 0x1f
# CHECK: vcmptrue_ussd
0xc5 0x07 0xc2 0xc7 0x1f
# CHECK: vcmpeq_uqps
0xc5 0x04 0xc2 0xc7 0x08
# CHECK: vcmpeq_uqpd
0xc5 0x05 0xc2 0xc7 0x08
# CHECK: vcmpeq_uqss
0xc5 0x06 0xc2 0xc7 0x08
# CHECK: vcmpeq_uqsd
0xc5 0x07 0xc2 0xc7 0x08
# CHECK: vcmpeqps
0xc5 0x04 0xc2 0xc7 0x00
# CHECK: vcmpeqpd
0xc5 0x05 0xc2 0xc7 0x00
# CHECK: vcmpeqss
0xc5 0x06 0xc2 0xc7 0x00
# CHECK: vcmpeqsd
0xc5 0x07 0xc2 0xc7 0x00
# CHECK: cmpeqps
0x0f 0xc2 0xc7 0x00
# CHECK: cmpeqpd
0x66 0x0f 0xc2 0xc7 0x00
# CHECK: cmpeqss
0xf3 0x0f 0xc2 0xc7 0x00
# CHECK: cmpeqsd
0xf2 0x0f 0xc2 0xc7 0x00
# CHECK: cmpordps
0x0f 0xc2 0xc7 0x07
# CHECK: cmpordpd
0x66 0x0f 0xc2 0xc7 0x07
# CHECK: cmpordss
0xf3 0x0f 0xc2 0xc7 0x07
# CHECK: cmpordsd
0xf2 0x0f 0xc2 0xc7 0x07
# CHECK: extrq $2, $3, %xmm0
0x66 0x0f 0x78 0xc0 0x03 0x02
# CHECK: extrq %xmm1, %xmm0
0x66 0x0f 0x79 0xc1
# CHECK: insertq $6, $5, %xmm1, %xmm0
0xf2 0x0f 0x78 0xc1 0x05 0x06
# CHECK: insertq %xmm1, %xmm0
0xf2 0x0f 0x79 0xc1
# CHECK: movntsd %xmm0, (%rdi)
0xf2 0x0f 0x2b 0x07
# CHECK: movntss %xmm0, (%rdi)
0xf3 0x0f 0x2b 0x07