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26160f4e64
the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
609 B
LLVM
20 lines
609 B
LLVM
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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; This verifies that we generate correct spill/reload code for vector regs.
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define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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%w.addr = alloca <4 x float>, align 16
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store i32 %i, i32* %i.addr, align 4
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store <4 x float> %w, <4 x float>* %w.addr, align 16
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call void @foo(i32* %i.addr)
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ret void
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}
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; CHECK: stvx 2, 0, 0
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; CHECK: lvx 2, 0, 0
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declare void @foo(i32*)
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