David Woodhouse 2634d1f6da [x86] Do not relax PUSHi16 to PUSHi32 (PR18414) ... They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198761 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-08 12:58:32 +00:00
..
AArch64	[AArch64][NEON] Added SXTL and SXTL2 instruction aliases	2014-01-03 19:20:31 +00:00
ARM	ARM IAS: properly handle expression operands	2014-01-08 03:28:14 +00:00
AsmParser	Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.	2014-01-05 01:35:51 +00:00
COFF	Add the .secidx test I've forgotten to svn add in 197826	2013-12-20 19:06:50 +00:00
Disassembler	[Sparc] Add support for parsing branch instructions and conditional moves.	2014-01-08 06:14:52 +00:00
ELF	In the ELFWriter when writing aliased (.set) symbols dont blindly	2014-01-07 20:17:03 +00:00
MachO	Fixed a bug in getARMFixupKindMachOInfo() where three ARM fixup kinds	2013-12-13 22:46:54 +00:00
Markup
Mips	[Mips] TargetStreamer Support for .abicalls and .set pic0.	2014-01-06 23:27:31 +00:00
PowerPC
Sparc	[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.	2014-01-08 07:47:57 +00:00
SystemZ	[SystemZ] Add MC support for interlocked-access 1 instructions	2013-12-24 15:14:05 +00:00
X86	[x86] Do not relax PUSHi16 to PUSHi32 (PR18414)	2014-01-08 12:58:32 +00:00