Bill Wendling 54a56fad36 Don't cache the instruction and register info from the TargetMachine, because ...

the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-07 06:19:56 +00:00

..

InstPrinter

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MCTargetDesc

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TargetInfo

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CMakeLists.txt

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Hexagon.h

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Hexagon.td

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HexagonAsmPrinter.cpp

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HexagonAsmPrinter.h

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HexagonCallingConv.td

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HexagonCallingConvLower.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonCallingConvLower.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonCFGOptimizer.cpp

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HexagonCopyToCombine.cpp

Hexagon: Typo fix.

2013-05-28 19:01:45 +00:00

HexagonExpandPredSpillCode.cpp

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HexagonFixupHwLoops.cpp

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HexagonFrameLowering.cpp

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HexagonFrameLowering.h

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HexagonHardwareLoops.cpp

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HexagonInstrFormats.td

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HexagonInstrFormatsV4.td

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HexagonInstrInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonInstrInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonInstrInfo.td

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HexagonInstrInfoV3.td

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HexagonInstrInfoV4.td

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HexagonInstrInfoV5.td

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HexagonIntrinsics.td

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HexagonIntrinsicsDerived.td

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HexagonIntrinsicsV3.td

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HexagonIntrinsicsV4.td

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HexagonIntrinsicsV5.td

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HexagonISelDAGToDAG.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonISelLowering.cpp

Order CALLSEQ_START and CALLSEQ_END nodes.

2013-05-29 22:03:55 +00:00

HexagonISelLowering.h

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

HexagonMachineFunctionInfo.h

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HexagonMachineScheduler.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonMachineScheduler.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonMCInstLower.cpp

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HexagonNewValueJump.cpp

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HexagonOperands.td

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HexagonPeephole.cpp

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HexagonRegisterInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonRegisterInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonRegisterInfo.td

Make SubRegIndex size mandatory, following r183020.

2013-05-31 23:45:26 +00:00

HexagonRemoveSZExtArgs.cpp

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HexagonSchedule.td

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HexagonScheduleV4.td

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HexagonSelectCCInfo.td

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HexagonSelectionDAGInfo.cpp

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

HexagonSelectionDAGInfo.h

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

HexagonSplitConst32AndConst64.cpp

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HexagonSplitTFRCondSets.cpp

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HexagonSubtarget.cpp

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HexagonSubtarget.h

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HexagonTargetMachine.cpp

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HexagonTargetMachine.h

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HexagonTargetObjectFile.cpp

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HexagonTargetObjectFile.h

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HexagonVarargsCallingConvention.h

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HexagonVLIWPacketizer.cpp

Hexagon: Make helper functions static.

2013-05-23 15:43:11 +00:00

LLVMBuild.txt

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Makefile

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