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276365dd4b
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.0 KiB
C++
59 lines
2.0 KiB
C++
//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CellSPU-specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "SPUSubtarget.h"
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#include "SPU.h"
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#include "SPUGenSubtarget.inc"
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#include "llvm/ADT/SmallVector.h"
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#include "SPURegisterInfo.h"
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using namespace llvm;
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SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS) :
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StackAlignment(16),
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ProcDirective(SPU::DEFAULT_PROC),
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UseLargeMem(false)
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{
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// Should be the target SPU processor type. For now, since there's only
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// one, simply default to the current "v0" default:
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std::string default_cpu("v0");
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// Parse features string.
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ParseSubtargetFeatures(FS, default_cpu);
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}
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/// SetJITMode - This is called to inform the subtarget info that we are
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/// producing code for the JIT.
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void SPUSubtarget::SetJITMode() {
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}
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/// Enable PostRA scheduling for optimization levels -O2 and -O3.
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bool SPUSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtarget::ANTIDEP_CRITICAL;
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// CriticalPathsRCs seems to be the set of
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// RegisterClasses that antidep breakings are performed for.
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// Do it for all register classes
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(&SPU::R8CRegClass);
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CriticalPathRCs.push_back(&SPU::R16CRegClass);
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CriticalPathRCs.push_back(&SPU::R32CRegClass);
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CriticalPathRCs.push_back(&SPU::R32FPRegClass);
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CriticalPathRCs.push_back(&SPU::R64CRegClass);
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CriticalPathRCs.push_back(&SPU::VECREGRegClass);
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return OptLevel >= CodeGenOpt::Default;
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}
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