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276b77e66c
register is available and when it's profitable. e.g. xorq %r12<kill>, %r13 addq %rax, -184(%rbp) addq %r13, -184(%rbp) ==> xorq %r12<kill>, %r13 movq -184(%rbp), %r12 addq %rax, %r12 addq %r13, %r12 movq %r12, -184(%rbp) Two more instructions, but fewer memory accesses. It can also open up opportunities for more optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69341 91177308-0d34-0410-b5e6-96231b3b80d8 |
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Alpha | ||
ARM | ||
CBackend | ||
CellSPU | ||
CPP | ||
Generic | ||
IA64 | ||
Mips | ||
PowerPC | ||
SPARC | ||
X86 | ||
XCore |