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https://github.com/c64scene-ar/llvm-6502.git
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f7331b3dd7
init_trampoline. There is now only one trampoline intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
1141 lines
43 KiB
C++
1141 lines
43 KiB
C++
//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the SPARC target.
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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namespace SPISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
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CMPICC, // Compare two GPR operands, set icc.
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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SELECT_ICC, // Select between two values using the current ICC flags.
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SELECT_FCC, // Select between two values using the current FCC flags.
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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CALL, // A call instruction.
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RET_FLAG // Return with a flag operand.
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};
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}
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/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
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/// condition.
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static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: return SPCC::ICC_E;
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case ISD::SETNE: return SPCC::ICC_NE;
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case ISD::SETLT: return SPCC::ICC_L;
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case ISD::SETGT: return SPCC::ICC_G;
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case ISD::SETLE: return SPCC::ICC_LE;
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case ISD::SETGE: return SPCC::ICC_GE;
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case ISD::SETULT: return SPCC::ICC_CS;
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case ISD::SETULE: return SPCC::ICC_LEU;
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case ISD::SETUGT: return SPCC::ICC_GU;
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case ISD::SETUGE: return SPCC::ICC_CC;
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}
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}
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/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
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/// FCC condition.
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static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown fp condition code!");
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case ISD::SETEQ:
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case ISD::SETOEQ: return SPCC::FCC_E;
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case ISD::SETNE:
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case ISD::SETUNE: return SPCC::FCC_NE;
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case ISD::SETLT:
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case ISD::SETOLT: return SPCC::FCC_L;
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case ISD::SETGT:
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case ISD::SETOGT: return SPCC::FCC_G;
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case ISD::SETLE:
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case ISD::SETOLE: return SPCC::FCC_LE;
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case ISD::SETGE:
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case ISD::SETOGE: return SPCC::FCC_GE;
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case ISD::SETULT: return SPCC::FCC_UL;
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case ISD::SETULE: return SPCC::FCC_ULE;
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case ISD::SETUGT: return SPCC::FCC_UG;
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case ISD::SETUGE: return SPCC::FCC_UGE;
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case ISD::SETUO: return SPCC::FCC_U;
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case ISD::SETO: return SPCC::FCC_O;
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case ISD::SETONE: return SPCC::FCC_LG;
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case ISD::SETUEQ: return SPCC::FCC_UE;
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}
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}
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namespace {
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class SparcTargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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public:
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SparcTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
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bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG);
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
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// Turn FP extload into load/fextend
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setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// Expand fp<->uint
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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// Sparc doesn't have BRCOND either, it has BR_CC.
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// SPARC has no intrinsics for these particular operations.
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// RET must be custom lowered, to meet ABI requirements
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setOperationAction(ISD::RET , MVT::Other, Custom);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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// VAARG needs to be lowered to not do unaligned accesses for doubles.
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setOperationAction(ISD::VAARG , MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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setStackPointerRegisterToSaveRestore(SP::O6);
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if (TM.getSubtarget<SparcSubtarget>().isV9()) {
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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}
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computeRegisterProperties();
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}
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const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case SPISD::CMPICC: return "SPISD::CMPICC";
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case SPISD::CMPFCC: return "SPISD::CMPFCC";
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case SPISD::BRICC: return "SPISD::BRICC";
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case SPISD::BRFCC: return "SPISD::BRFCC";
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case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
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case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
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case SPISD::Hi: return "SPISD::Hi";
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case SPISD::Lo: return "SPISD::Lo";
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case SPISD::FTOI: return "SPISD::FTOI";
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case SPISD::ITOF: return "SPISD::ITOF";
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case SPISD::CALL: return "SPISD::CALL";
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case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
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}
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}
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/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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/// be zero. Op is expected to be a target specific node. Used by DAG
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/// combiner.
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void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const {
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uint64_t KnownZero2, KnownOne2;
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KnownZero = KnownOne = 0; // Don't know anything.
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switch (Op.getOpcode()) {
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default: break;
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case SPISD::SELECT_ICC:
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case SPISD::SELECT_FCC:
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DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
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Depth+1);
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DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
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Depth+1);
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// Only known if known in both the LHS and RHS.
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KnownOne &= KnownOne2;
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KnownZero &= KnownZero2;
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break;
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}
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}
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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std::vector<SDOperand>
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SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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SDOperand Root = DAG.getRoot();
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std::vector<SDOperand> OutChains;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = ISD::AssertSext;
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Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
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DAG.getValueType(ObjectVT));
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Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
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}
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ArgValues.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
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} else {
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ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
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FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
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NULL, 0, ObjectVT);
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Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
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}
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ArgValues.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
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ArgValues.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
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ArgValues.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (/* FIXME: Apparently this isn't safe?? */
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0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
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((CurArgReg-ArgRegs) & 1) == 0) {
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// If this is a double argument and the whole thing lives on the stack,
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// and the argument is aligned, load the double straight from the stack.
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// We can't do a load in cases like void foo([6ints], int,double),
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// because the double wouldn't be aligned!
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
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} else {
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SDOperand HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
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}
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SDOperand LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
|
|
unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
|
|
MF.addLiveIn(*CurArgReg++, VRegLo);
|
|
LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
|
|
} else {
|
|
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
|
|
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
|
|
LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
|
|
}
|
|
|
|
// Compose the two halves together into an i64 unit.
|
|
SDOperand WholeValue =
|
|
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
|
|
|
|
// If we want a double, do a bit convert.
|
|
if (ObjectVT == MVT::f64)
|
|
WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
|
|
|
|
ArgValues.push_back(WholeValue);
|
|
}
|
|
ArgOffset += 8;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Store remaining ArgRegs to the stack if this is a varargs function.
|
|
if (F.getFunctionType()->isVarArg()) {
|
|
// Remember the vararg offset for the va_start implementation.
|
|
VarArgsFrameOffset = ArgOffset;
|
|
|
|
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
|
|
unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
|
|
MF.addLiveIn(*CurArgReg, VReg);
|
|
SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
|
|
|
|
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
|
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
|
|
|
|
OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
|
|
ArgOffset += 4;
|
|
}
|
|
}
|
|
|
|
if (!OutChains.empty())
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
&OutChains[0], OutChains.size()));
|
|
|
|
// Finally, inform the code generator which regs we return values in.
|
|
switch (getValueType(F.getReturnType())) {
|
|
default: assert(0 && "Unknown type!");
|
|
case MVT::isVoid: break;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
MF.addLiveOut(SP::I0);
|
|
break;
|
|
case MVT::i64:
|
|
MF.addLiveOut(SP::I0);
|
|
MF.addLiveOut(SP::I1);
|
|
break;
|
|
case MVT::f32:
|
|
MF.addLiveOut(SP::F0);
|
|
break;
|
|
case MVT::f64:
|
|
MF.addLiveOut(SP::D0);
|
|
break;
|
|
}
|
|
|
|
return ArgValues;
|
|
}
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
|
|
bool RetTyIsSigned, bool isVarArg, unsigned CC,
|
|
bool isTailCall, SDOperand Callee,
|
|
ArgListTy &Args, SelectionDAG &DAG) {
|
|
// Count the size of the outgoing arguments.
|
|
unsigned ArgsSize = 0;
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
switch (getValueType(Args[i].Ty)) {
|
|
default: assert(0 && "Unknown value type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::f32:
|
|
ArgsSize += 4;
|
|
break;
|
|
case MVT::i64:
|
|
case MVT::f64:
|
|
ArgsSize += 8;
|
|
break;
|
|
}
|
|
}
|
|
if (ArgsSize > 4*6)
|
|
ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
|
|
else
|
|
ArgsSize = 0;
|
|
|
|
// Keep stack frames 8-byte aligned.
|
|
ArgsSize = (ArgsSize+7) & ~7;
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
|
|
|
|
SDOperand StackPtr;
|
|
std::vector<SDOperand> Stores;
|
|
std::vector<SDOperand> RegValuesToPass;
|
|
unsigned ArgOffset = 68;
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
SDOperand Val = Args[i].Node;
|
|
MVT::ValueType ObjectVT = Val.getValueType();
|
|
SDOperand ValToStore(0, 0);
|
|
unsigned ObjSize;
|
|
switch (ObjectVT) {
|
|
default: assert(0 && "Unhandled argument type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16: {
|
|
// Promote the integer to 32-bits. If the input type is signed, use a
|
|
// sign extend, otherwise use a zero extend.
|
|
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
|
|
if (Args[i].isSExt)
|
|
ExtendKind = ISD::SIGN_EXTEND;
|
|
else if (Args[i].isZExt)
|
|
ExtendKind = ISD::ZERO_EXTEND;
|
|
Val = DAG.getNode(ExtendKind, MVT::i32, Val);
|
|
// FALL THROUGH
|
|
}
|
|
case MVT::i32:
|
|
ObjSize = 4;
|
|
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val;
|
|
} else {
|
|
RegValuesToPass.push_back(Val);
|
|
}
|
|
break;
|
|
case MVT::f32:
|
|
ObjSize = 4;
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val;
|
|
} else {
|
|
// Convert this to a FP value in an int reg.
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
|
|
RegValuesToPass.push_back(Val);
|
|
}
|
|
break;
|
|
case MVT::f64:
|
|
ObjSize = 8;
|
|
// If we can store this directly into the outgoing slot, do so. We can
|
|
// do this when all ArgRegs are used and if the outgoing slot is aligned.
|
|
// FIXME: McGill/misr fails with this.
|
|
if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
|
|
ValToStore = Val;
|
|
break;
|
|
}
|
|
|
|
// Otherwise, convert this to a FP value in int regs.
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
|
|
// FALL THROUGH
|
|
case MVT::i64:
|
|
ObjSize = 8;
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val; // Whole thing is passed in memory.
|
|
break;
|
|
}
|
|
|
|
// Split the value into top and bottom part. Top part goes in a reg.
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
|
|
DAG.getConstant(1, MVT::i32));
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
|
|
DAG.getConstant(0, MVT::i32));
|
|
RegValuesToPass.push_back(Hi);
|
|
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Lo;
|
|
ArgOffset += 4;
|
|
ObjSize = 4;
|
|
} else {
|
|
RegValuesToPass.push_back(Lo);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (ValToStore.Val) {
|
|
if (!StackPtr.Val) {
|
|
StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
|
}
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
|
|
}
|
|
ArgOffset += ObjSize;
|
|
}
|
|
|
|
// Emit all stores, make sure the occur before any copies into physregs.
|
|
if (!Stores.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
|
|
|
|
static const unsigned ArgRegs[] = {
|
|
SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
|
|
};
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
// and flag operands which copy the outgoing args into O[0-5].
|
|
SDOperand InFlag;
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
// Likewise ExternalSymbol -> TargetExternalSymbol.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
|
|
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
|
|
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
|
|
|
|
std::vector<MVT::ValueType> NodeTys;
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
SDOperand Ops[] = { Chain, Callee, InFlag };
|
|
Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
SDOperand RetVal;
|
|
if (RetTyVT != MVT::isVoid) {
|
|
switch (RetTyVT) {
|
|
default: assert(0 && "Unknown value type to return!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16: {
|
|
RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
|
|
// Add a note to keep track of whether it is sign or zero extended.
|
|
ISD::NodeType AssertKind = ISD::AssertZext;
|
|
if (RetTyIsSigned)
|
|
AssertKind = ISD::AssertSext;
|
|
RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
|
|
DAG.getValueType(RetTyVT));
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
|
|
break;
|
|
}
|
|
case MVT::i32:
|
|
RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::f32:
|
|
RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::f64:
|
|
RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::i64:
|
|
SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
|
|
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
|
|
Lo.getValue(2));
|
|
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
|
|
Chain = Hi.getValue(1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
|
|
DAG.getConstant(ArgsSize, getPointerTy()));
|
|
|
|
return std::make_pair(RetVal, Chain);
|
|
}
|
|
|
|
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
|
|
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
|
|
static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
|
|
ISD::CondCode CC, unsigned &SPCC) {
|
|
if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
|
|
CC == ISD::SETNE &&
|
|
((LHS.getOpcode() == SPISD::SELECT_ICC &&
|
|
LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
|
|
(LHS.getOpcode() == SPISD::SELECT_FCC &&
|
|
LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
|
|
isa<ConstantSDNode>(LHS.getOperand(0)) &&
|
|
isa<ConstantSDNode>(LHS.getOperand(1)) &&
|
|
cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
|
|
cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
|
|
SDOperand CMPCC = LHS.getOperand(3);
|
|
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
|
|
LHS = CMPCC.getOperand(0);
|
|
RHS = CMPCC.getOperand(1);
|
|
}
|
|
}
|
|
|
|
|
|
SDOperand SparcTargetLowering::
|
|
LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Should not custom lower this!");
|
|
case ISD::GlobalTLSAddress:
|
|
assert(0 && "TLS not implemented for Sparc.");
|
|
case ISD::GlobalAddress: {
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
|
|
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
|
|
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
|
|
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
|
|
}
|
|
case ISD::ConstantPool: {
|
|
Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
|
|
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
|
|
cast<ConstantPoolSDNode>(Op)->getAlignment());
|
|
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
|
|
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
|
|
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
|
|
}
|
|
case ISD::FP_TO_SINT:
|
|
// Convert the fp value to integer in an FP register.
|
|
assert(Op.getValueType() == MVT::i32);
|
|
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
|
|
case ISD::SINT_TO_FP: {
|
|
assert(Op.getOperand(0).getValueType() == MVT::i32);
|
|
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
|
|
// Convert the int value to FP in an FP register.
|
|
return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
|
|
}
|
|
case ISD::BR_CC: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDOperand LHS = Op.getOperand(2);
|
|
SDOperand RHS = Op.getOperand(3);
|
|
SDOperand Dest = Op.getOperand(4);
|
|
unsigned Opc, SPCC = ~0U;
|
|
|
|
// If this is a br_cc of a "setcc", and if the setcc got lowered into
|
|
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
|
|
LookThroughSetCC(LHS, RHS, CC, SPCC);
|
|
|
|
// Get the condition flag.
|
|
SDOperand CompareFlag;
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<MVT::ValueType> VTs;
|
|
VTs.push_back(MVT::i32);
|
|
VTs.push_back(MVT::Flag);
|
|
SDOperand Ops[2] = { LHS, RHS };
|
|
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
|
|
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
|
|
Opc = SPISD::BRICC;
|
|
} else {
|
|
CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
|
|
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
|
Opc = SPISD::BRFCC;
|
|
}
|
|
return DAG.getNode(Opc, MVT::Other, Chain, Dest,
|
|
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
|
}
|
|
case ISD::SELECT_CC: {
|
|
SDOperand LHS = Op.getOperand(0);
|
|
SDOperand RHS = Op.getOperand(1);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDOperand TrueVal = Op.getOperand(2);
|
|
SDOperand FalseVal = Op.getOperand(3);
|
|
unsigned Opc, SPCC = ~0U;
|
|
|
|
// If this is a select_cc of a "setcc", and if the setcc got lowered into
|
|
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
|
|
LookThroughSetCC(LHS, RHS, CC, SPCC);
|
|
|
|
SDOperand CompareFlag;
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<MVT::ValueType> VTs;
|
|
VTs.push_back(LHS.getValueType()); // subcc returns a value
|
|
VTs.push_back(MVT::Flag);
|
|
SDOperand Ops[2] = { LHS, RHS };
|
|
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
|
|
Opc = SPISD::SELECT_ICC;
|
|
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
|
|
} else {
|
|
CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
|
|
Opc = SPISD::SELECT_FCC;
|
|
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
|
}
|
|
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
|
|
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
|
}
|
|
case ISD::VASTART: {
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
|
|
DAG.getRegister(SP::I6, MVT::i32),
|
|
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
|
|
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
|
return DAG.getStore(Op.getOperand(0), Offset,
|
|
Op.getOperand(1), SV->getValue(), SV->getOffset());
|
|
}
|
|
case ISD::VAARG: {
|
|
SDNode *Node = Op.Val;
|
|
MVT::ValueType VT = Node->getValueType(0);
|
|
SDOperand InChain = Node->getOperand(0);
|
|
SDOperand VAListPtr = Node->getOperand(1);
|
|
SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
|
|
SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
|
|
SV->getValue(), SV->getOffset());
|
|
// Increment the pointer, VAList, to the next vaarg
|
|
SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
|
|
DAG.getConstant(MVT::getSizeInBits(VT)/8,
|
|
getPointerTy()));
|
|
// Store the incremented VAList to the legalized pointer
|
|
InChain = DAG.getStore(VAList.getValue(1), NextPtr,
|
|
VAListPtr, SV->getValue(), SV->getOffset());
|
|
// Load the actual argument out of the pointer VAList, unless this is an
|
|
// f64 load.
|
|
if (VT != MVT::f64) {
|
|
return DAG.getLoad(VT, InChain, VAList, NULL, 0);
|
|
} else {
|
|
// Otherwise, load it as i64, then do a bitconvert.
|
|
SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
|
|
std::vector<MVT::ValueType> Tys;
|
|
Tys.push_back(MVT::f64);
|
|
Tys.push_back(MVT::Other);
|
|
// Bit-Convert the value to f64.
|
|
SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
|
|
V.getValue(1) };
|
|
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
|
|
}
|
|
}
|
|
case ISD::DYNAMIC_STACKALLOC: {
|
|
SDOperand Chain = Op.getOperand(0); // Legalize the chain.
|
|
SDOperand Size = Op.getOperand(1); // Legalize the size.
|
|
|
|
unsigned SPReg = SP::O6;
|
|
SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
|
|
SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
|
|
Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
|
|
|
|
// The resultant pointer is actually 16 words from the bottom of the stack,
|
|
// to provide a register spill area.
|
|
SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
|
|
DAG.getConstant(96, MVT::i32));
|
|
std::vector<MVT::ValueType> Tys;
|
|
Tys.push_back(MVT::i32);
|
|
Tys.push_back(MVT::Other);
|
|
SDOperand Ops[2] = { NewVal, Chain };
|
|
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
|
|
}
|
|
case ISD::RET: {
|
|
SDOperand Copy;
|
|
|
|
switch(Op.getNumOperands()) {
|
|
default:
|
|
assert(0 && "Do not know how to return this many arguments!");
|
|
abort();
|
|
case 1:
|
|
return SDOperand(); // ret void is legal
|
|
case 3: {
|
|
unsigned ArgReg;
|
|
switch(Op.getOperand(1).getValueType()) {
|
|
default: assert(0 && "Unknown type to return!");
|
|
case MVT::i32: ArgReg = SP::I0; break;
|
|
case MVT::f32: ArgReg = SP::F0; break;
|
|
case MVT::f64: ArgReg = SP::D0; break;
|
|
}
|
|
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
|
|
SDOperand());
|
|
break;
|
|
}
|
|
case 5:
|
|
Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
|
|
SDOperand());
|
|
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
|
|
break;
|
|
}
|
|
return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
|
|
}
|
|
// Frame & Return address. Currently unimplemented
|
|
case ISD::RETURNADDR: break;
|
|
case ISD::FRAMEADDR: break;
|
|
}
|
|
return SDOperand();
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
MachineBasicBlock *BB) {
|
|
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
|
|
unsigned BROpcode;
|
|
unsigned CC;
|
|
// Figure out the conditional branch opcode to use for this select_cc.
|
|
switch (MI->getOpcode()) {
|
|
default: assert(0 && "Unknown SELECT_CC!");
|
|
case SP::SELECT_CC_Int_ICC:
|
|
case SP::SELECT_CC_FP_ICC:
|
|
case SP::SELECT_CC_DFP_ICC:
|
|
BROpcode = SP::BCOND;
|
|
break;
|
|
case SP::SELECT_CC_Int_FCC:
|
|
case SP::SELECT_CC_FP_FCC:
|
|
case SP::SELECT_CC_DFP_FCC:
|
|
BROpcode = SP::FBCOND;
|
|
break;
|
|
}
|
|
|
|
CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
++It;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// [f]bCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
|
BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
|
|
MachineFunction *F = BB->getParent();
|
|
F->getBasicBlockList().insert(It, copy0MBB);
|
|
F->getBasicBlockList().insert(It, sinkMBB);
|
|
// Update machine-CFG edges by first adding all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
|
|
e = BB->succ_end(); i != e; ++i)
|
|
sinkMBB->addSuccessor(*i);
|
|
// Next, remove all successors of the current block, and add the true
|
|
// and fallthrough blocks as its successors.
|
|
while(!BB->succ_empty())
|
|
BB->removeSuccessor(BB->succ_begin());
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
|
|
|
delete MI; // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Selector Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
|
|
/// instructions for SelectionDAG operations.
|
|
///
|
|
namespace {
|
|
class SparcDAGToDAGISel : public SelectionDAGISel {
|
|
SparcTargetLowering Lowering;
|
|
|
|
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const SparcSubtarget &Subtarget;
|
|
public:
|
|
SparcDAGToDAGISel(TargetMachine &TM)
|
|
: SelectionDAGISel(Lowering), Lowering(TM),
|
|
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
|
|
}
|
|
|
|
SDNode *Select(SDOperand Op);
|
|
|
|
// Complex Pattern Selectors.
|
|
bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
|
|
bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
|
|
SDOperand &Offset);
|
|
|
|
/// InstructionSelectBasicBlock - This callback is invoked by
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
|
|
|
|
virtual const char *getPassName() const {
|
|
return "SPARC DAG->DAG Pattern Instruction Selection";
|
|
}
|
|
|
|
// Include the pieces autogenerated from the target description.
|
|
#include "SparcGenDAGISel.inc"
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
/// InstructionSelectBasicBlock - This callback is invoked by
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
|
DEBUG(BB->dump());
|
|
|
|
// Select target instructions for the DAG.
|
|
DAG.setRoot(SelectRoot(DAG.getRoot()));
|
|
DAG.RemoveDeadNodes();
|
|
|
|
// Emit machine code to BB.
|
|
ScheduleAndEmitDAG(DAG);
|
|
}
|
|
|
|
bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
|
|
SDOperand &Base, SDOperand &Offset) {
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // direct calls.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
|
|
if (Predicate_simm13(CN)) {
|
|
if (FrameIndexSDNode *FIN =
|
|
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
|
|
// Constant offset from frame ref.
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
} else {
|
|
Base = Addr.getOperand(0);
|
|
}
|
|
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
|
|
return true;
|
|
}
|
|
}
|
|
if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
|
|
Base = Addr.getOperand(1);
|
|
Offset = Addr.getOperand(0).getOperand(0);
|
|
return true;
|
|
}
|
|
if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
|
|
Base = Addr.getOperand(0);
|
|
Offset = Addr.getOperand(1).getOperand(0);
|
|
return true;
|
|
}
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
|
|
SDOperand &R1, SDOperand &R2) {
|
|
if (Addr.getOpcode() == ISD::FrameIndex) return false;
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // direct calls.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
|
|
Predicate_simm13(Addr.getOperand(1).Val))
|
|
return false; // Let the reg+imm pattern catch this!
|
|
if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
|
|
Addr.getOperand(1).getOpcode() == SPISD::Lo)
|
|
return false; // Let the reg+imm pattern catch this!
|
|
R1 = Addr.getOperand(0);
|
|
R2 = Addr.getOperand(1);
|
|
return true;
|
|
}
|
|
|
|
R1 = Addr;
|
|
R2 = CurDAG->getRegister(SP::G0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
|
|
N->getOpcode() < SPISD::FIRST_NUMBER)
|
|
return NULL; // Already selected.
|
|
|
|
switch (N->getOpcode()) {
|
|
default: break;
|
|
case ISD::SDIV:
|
|
case ISD::UDIV: {
|
|
// FIXME: should use a custom expander to expose the SRA to the dag.
|
|
SDOperand DivLHS = N->getOperand(0);
|
|
SDOperand DivRHS = N->getOperand(1);
|
|
AddToISelQueue(DivLHS);
|
|
AddToISelQueue(DivRHS);
|
|
|
|
// Set the Y register to the high-part.
|
|
SDOperand TopPart;
|
|
if (N->getOpcode() == ISD::SDIV) {
|
|
TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
|
|
CurDAG->getTargetConstant(31, MVT::i32)), 0);
|
|
} else {
|
|
TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
|
|
}
|
|
TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
|
|
CurDAG->getRegister(SP::G0, MVT::i32)), 0);
|
|
|
|
// FIXME: Handle div by immediate.
|
|
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
|
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
|
|
TopPart);
|
|
}
|
|
case ISD::MULHU:
|
|
case ISD::MULHS: {
|
|
// FIXME: Handle mul by immediate.
|
|
SDOperand MulLHS = N->getOperand(0);
|
|
SDOperand MulRHS = N->getOperand(1);
|
|
AddToISelQueue(MulLHS);
|
|
AddToISelQueue(MulRHS);
|
|
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
|
|
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
|
|
MulLHS, MulRHS);
|
|
// The high part is in the Y register.
|
|
return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
|
|
/// createSparcISelDag - This pass converts a legalized DAG into a
|
|
/// SPARC-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
|
|
return new SparcDAGToDAGISel(TM);
|
|
}
|