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2516d0d7b1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97451 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.9 KiB
C++
73 lines
2.9 KiB
C++
//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target independent instruction opcodes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETOPCODES_H
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#define LLVM_TARGET_TARGETOPCODES_H
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namespace llvm {
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/// Invariant opcodes: All instruction sets have these as their low opcodes.
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namespace TargetOpcode {
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enum {
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PHI = 0,
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INLINEASM = 1,
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DBG_LABEL = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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KILL = 5,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// INSERT_SUBREG - This instruction takes three operands: a register
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/// that has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with
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/// the value of the second register inserted. The first register is
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/// often defined by an IMPLICIT_DEF, as is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
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/// that the first operand is an immediate integer constant. This constant
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/// is often zero, as is commonly used to implement zext operations on
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/// target architectures which support it, such as with x86-64 (with
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/// zext from i32 to i64 via implicit zero-extension).
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SUBREG_TO_REG = 9,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. The actual MachineInstrs to perform
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/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
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COPY_TO_REGCLASS = 10,
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DBG_VALUE = 11
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};
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} // end namespace TargetOpcode
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} // end namespace llvm
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#endif
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