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864e2efce2
MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
252 lines
8.3 KiB
C++
252 lines
8.3 KiB
C++
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSINSTRUCTIONINFO_H
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#define MIPSINSTRUCTIONINFO_H
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#include "Mips.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "MipsRegisterInfo.h"
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namespace llvm {
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namespace Mips {
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// Mips Branch Codes
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enum FPBranchCode {
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BRANCH_F,
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BRANCH_T,
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BRANCH_FL,
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BRANCH_TL,
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BRANCH_INVALID
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};
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// Mips Condition Codes
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enum CondCode {
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// To be used with float branch True
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FCOND_F,
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FCOND_UN,
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FCOND_EQ,
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FCOND_UEQ,
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FCOND_OLT,
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FCOND_ULT,
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FCOND_OLE,
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FCOND_ULE,
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FCOND_SF,
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FCOND_NGLE,
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FCOND_SEQ,
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FCOND_NGL,
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FCOND_LT,
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FCOND_NGE,
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FCOND_LE,
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FCOND_NGT,
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// To be used with float branch False
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// This conditions have the same mnemonic as the
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// above ones, but are used with a branch False;
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FCOND_T,
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FCOND_OR,
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FCOND_NEQ,
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FCOND_OGL,
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FCOND_UGE,
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FCOND_OGE,
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FCOND_UGT,
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FCOND_OGT,
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FCOND_ST,
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FCOND_GLE,
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FCOND_SNE,
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FCOND_GL,
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FCOND_NLT,
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FCOND_GE,
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FCOND_NLE,
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FCOND_GT,
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// Only integer conditions
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COND_E,
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COND_GZ,
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COND_GEZ,
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COND_LZ,
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COND_LEZ,
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COND_NE,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(Mips::CondCode CC);
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/// MipsCCToString - Map each FP condition code to its string
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inline static const char *MipsFCCToString(Mips::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case FCOND_F:
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case FCOND_T: return "f";
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case FCOND_UN:
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case FCOND_OR: return "un";
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case FCOND_EQ:
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case FCOND_NEQ: return "eq";
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case FCOND_UEQ:
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case FCOND_OGL: return "ueq";
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case FCOND_OLT:
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case FCOND_UGE: return "olt";
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case FCOND_ULT:
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case FCOND_OGE: return "ult";
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case FCOND_OLE:
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case FCOND_UGT: return "ole";
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case FCOND_ULE:
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case FCOND_OGT: return "ule";
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case FCOND_SF:
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case FCOND_ST: return "sf";
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case FCOND_NGLE:
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case FCOND_GLE: return "ngle";
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case FCOND_SEQ:
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case FCOND_SNE: return "seq";
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case FCOND_NGL:
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case FCOND_GL: return "ngl";
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case FCOND_LT:
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case FCOND_NLT: return "lt";
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case FCOND_NGE:
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case FCOND_GE: return "ge";
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case FCOND_LE:
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case FCOND_NLE: return "nle";
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case FCOND_NGT:
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case FCOND_GT: return "gt";
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}
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}
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}
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/// MipsII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MipsII {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// Mips Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_GOT - Represents the offset into the global offset table at which
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/// the address the relocation entry symbol resides during execution.
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MO_GOT,
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/// MO_GOT_CALL - Represents the offset into the global offset table at
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/// which the address of a call site relocation entry symbol resides
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/// during execution. This is different from the above since this flag
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/// can only be present in call instructions.
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MO_GOT_CALL,
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/// MO_GPREL - Represents the offset from the current gp value to be used
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/// for the relocatable object file being produced.
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MO_GPREL,
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/// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
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/// address.
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MO_ABS_HILO
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};
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}
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class MipsInstrInfo : public TargetInstrInfoImpl {
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MipsTargetMachine &TM;
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const MipsRegisterInfo RI;
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public:
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explicit MipsInstrInfo(MipsTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// Branch Analysis
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/// Insert nop instruction when hazard condition is found
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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};
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}
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#endif
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