Tim Northover 284c931330 ARM: fix fast-isel assertion failure ...

Missing braces on if meant we inserted both ARM and Thumb load for a litpool
entry. This didn't end well.

rdar://problem/15959157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200752 91177308-0d34-0410-b5e6-96231b3b80d8

2014-02-04 10:38:46 +00:00

..

AArch64

AArch64 & ARM: refactor crypto intrinsics to take scalars

2014-02-03 17:27:49 +00:00

ARM

ARM: fix fast-isel assertion failure

2014-02-04 10:38:46 +00:00

CPP

Begin adding docs and IR-level support for the inalloca attribute

2013-12-19 02:14:12 +00:00

Generic

Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory.

2014-01-27 09:43:10 +00:00

Hexagon

DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}

2014-02-04 01:23:52 +00:00

Inputs

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Mips

[mips][msa] Add insert.d instruction.

2014-01-31 13:31:20 +00:00

MSP430

Fix known typos

2014-01-24 17:20:08 +00:00

NVPTX

[NVPTX] Fix emitting aggregate parameters

2014-01-28 18:35:29 +00:00

PowerPC

DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}

2014-02-04 01:23:52 +00:00

R600

R600/SI: Fix fneg for 0.0

2014-02-04 07:12:38 +00:00

SPARC

[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.

2014-02-01 18:54:16 +00:00

SystemZ

XFAIL test/CodeGen/SystemZ/alias-01.ll which requires CodeGen TBAA

2014-01-25 19:31:44 +00:00

Thumb

CodeGen: Stop treating vectors as aggregates

2014-01-21 22:46:46 +00:00

Thumb2

PGO branch weight: update edge weights in IfConverter.

2014-01-29 23:18:47 +00:00

X86

DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}

2014-02-04 01:23:52 +00:00

XCore

Fix broken CHECK lines.

2014-01-11 21:06:00 +00:00