Andrew Lenharth dd3ccde9ea it helps if your conditionals are not reversed ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24641 91177308-0d34-0410-b5e6-96231b3b80d8

2005-12-09 00:45:42 +00:00

..

.cvsignore

…

Alpha.h

…

Alpha.td

…

AlphaAsmPrinter.cpp

No longer track value types for asm printer operands, and remove them as

2005-11-30 18:54:35 +00:00

AlphaCodeEmitter.cpp

massive DAGISel patch. lots and lots more stuff compiles now

2005-11-22 04:20:06 +00:00

AlphaInstrFormats.td

OK, this does wonders for broken stuff

2005-12-06 20:40:34 +00:00

AlphaInstrInfo.cpp

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaInstrInfo.h

…

AlphaInstrInfo.td

it helps if your conditionals are not reversed

2005-12-09 00:45:42 +00:00

AlphaISelDAGToDAG.cpp

fix divide and remainder

2005-12-06 23:27:39 +00:00

AlphaISelLowering.cpp

Make typesafe that which isn't: FCMOVxx

2005-11-30 17:11:20 +00:00

AlphaISelLowering.h

FPSelect and more custom lowering

2005-11-30 16:10:29 +00:00

AlphaISelPattern.cpp

major think-o

2005-12-01 17:48:51 +00:00

AlphaJITInfo.cpp

…

AlphaJITInfo.h

…

AlphaRegisterInfo.cpp

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaRegisterInfo.h

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaRegisterInfo.td

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

AlphaRelocations.h

…

AlphaSubtarget.cpp

…

AlphaSubtarget.h

…

AlphaTargetMachine.cpp

prevent latent switch creation

2005-11-18 13:57:03 +00:00

AlphaTargetMachine.h

…

Makefile

…