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https://github.com/c64scene-ar/llvm-6502.git
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d7802bf0dd
on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
257 lines
9.9 KiB
C++
257 lines
9.9 KiB
C++
//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPCMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCBaseInfo.h"
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class PPCMCCodeEmitter : public MCCodeEmitter {
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PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCSubtargetInfo &STI;
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Triple TT;
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public:
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PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
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MCContext &ctx)
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: STI(sti), TT(STI.getTargetTriple()) {
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}
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~PPCMCCodeEmitter() {}
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bool is64BitMode() const {
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return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
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}
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bool isSVR4ABI() const {
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return TT.isMacOSX() == 0;
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}
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unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
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// BL8_NOPELF and BLA8_NOP_ELF is both size of 8 bacause of the
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// following 'nop'.
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unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
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unsigned Opcode = MI.getOpcode();
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if (Opcode == PPC::BL8_NOP_ELF || Opcode == PPC::BLA8_NOP_ELF)
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Size = 8;
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// Output the constant in big endian byte order.
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int ShiftValue = (Size * 8) - 8;
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for (unsigned i = 0; i != Size; ++i) {
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OS << (char)(Bits >> ShiftValue);
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Bits <<= 8;
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCMCCodeEmitter(MCII, STI, Ctx);
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}
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unsigned PPCMCCodeEmitter::
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getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_br24));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_ha16));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Encode (imm, reg) as a memri, which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
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// Add a fixup for the displacement field.
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if (isSVR4ABI() && is64BitMode())
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16));
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else
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Encode (imm, reg) as a memrix, which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
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// Add a fixup for the branch target.
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if (isSVR4ABI() && is64BitMode())
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16_ds));
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else
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo14));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// Add a fixup for the GOT displacement to the TLS block offset.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16_ds));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the TLS register, which simply provides a relocation
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// hint to the linker that this statement is part of a relocation sequence.
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// Return the thread-pointer register's encoding.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_tlsreg));
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return getPPCRegisterNumbering(PPC::X13);
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}
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unsigned PPCMCCodeEmitter::
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get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert((MI.getOpcode() == PPC::MTCRF ||
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MI.getOpcode() == PPC::MFOCRF ||
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MI.getOpcode() == PPC::MTCRF8) &&
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(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
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return 0x80 >> getPPCRegisterNumbering(MO.getReg());
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}
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unsigned PPCMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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// MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
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// The GPR operand should come through here though.
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assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
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MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
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return getPPCRegisterNumbering(MO.getReg());
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}
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assert(MO.isImm() &&
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"Relocation required in an instruction that we cannot encode!");
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return MO.getImm();
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}
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#include "PPCGenMCCodeEmitter.inc"
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