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The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
889 B
LLVM
29 lines
889 B
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movdq2q | count 2
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; Since the add is not an MMX add, we don't have a movq2dq any more.
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@g_v8qi = external global <8 x i8>
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define void @t1() nounwind {
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%tmp3 = load <8 x i8>* @g_v8qi, align 8
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%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
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%tmp4 = tail call i32 (...)* @pass_v8qi( x86_mmx %tmp3a ) nounwind
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ret void
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}
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define void @t2(x86_mmx %v1, x86_mmx %v2) nounwind {
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%v1a = bitcast x86_mmx %v1 to <8 x i8>
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%v2b = bitcast x86_mmx %v2 to <8 x i8>
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%tmp3 = add <8 x i8> %v1a, %v2b
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%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
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%tmp4 = tail call i32 (...)* @pass_v8qi( x86_mmx %tmp3a ) nounwind
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ret void
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}
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define void @t3() nounwind {
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call void @pass_v1di( <1 x i64> zeroinitializer )
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ret void
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}
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declare i32 @pass_v8qi(...)
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declare void @pass_v1di(<1 x i64>)
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