Richard Osborne 29cab5f0ee Add pseudo instructions to the XCore for (load|store|load address) of a ... frame index. eliminateFrameIndex will replace these instructions with (LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use. This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame pointer elimination. However since they were marked as implicitly using SP they could not be rematerialised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-14 18:26:46 +00:00
..
Alpha
ARM	Clean up some ARM GV asm printing out; minor fixes to match what gcc does.	2008-12-06 02:00:55 +00:00
CBackend
CellSPU	Fix off-by-one error in traversing an array; this fixes a test.	2009-01-07 23:07:29 +00:00
CPP
Generic	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
IA64
Mips	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
PowerPC	this test should not run opt -std-compile-opts, it should run	2009-01-09 05:32:00 +00:00
SPARC
X86	Disable the register+memory forms of the bt instructions for now. Thanks	2009-01-13 23:23:30 +00:00
XCore	Add pseudo instructions to the XCore for (load|store|load address) of a	2009-01-14 18:26:46 +00:00