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044f841267
In preparation for the addition of other SIMD ISA extensions (such as QPX) we need to make sure that all Altivec patterns are properly predicated on having Altivec support. No functionality change intended (one test case needed to be updated b/c it assumed that Altivec intrinsics would be supported without enabling Altivec support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
607 B
LLVM
16 lines
607 B
LLVM
; RUN: llc < %s -march=ppc64 -mattr=+altivec | grep dst | count 4
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define hidden void @_Z4borkPc(i8* %image) {
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entry:
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tail call void @llvm.ppc.altivec.dst( i8* %image, i32 8, i32 0 )
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tail call void @llvm.ppc.altivec.dstt( i8* %image, i32 8, i32 0 )
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tail call void @llvm.ppc.altivec.dstst( i8* %image, i32 8, i32 0 )
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tail call void @llvm.ppc.altivec.dststt( i8* %image, i32 8, i32 0 )
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ret void
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}
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declare void @llvm.ppc.altivec.dst(i8*, i32, i32)
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declare void @llvm.ppc.altivec.dstt(i8*, i32, i32)
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declare void @llvm.ppc.altivec.dstst(i8*, i32, i32)
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declare void @llvm.ppc.altivec.dststt(i8*, i32, i32)
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