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4647919784
The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.0 KiB
LLVM
53 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @foo(i64 %a) nounwind {
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entry:
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%x = sitofp i64 %a to float
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ret float %x
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; CHECK: @foo
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfids 1, [[REG]]
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; CHECK: blr
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}
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define double @goo(i64 %a) nounwind {
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entry:
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%x = sitofp i64 %a to double
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ret double %x
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; CHECK: @goo
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfid 1, [[REG]]
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; CHECK: blr
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}
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define float @foou(i64 %a) nounwind {
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entry:
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%x = uitofp i64 %a to float
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ret float %x
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; CHECK: @foou
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfidus 1, [[REG]]
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; CHECK: blr
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}
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define double @goou(i64 %a) nounwind {
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entry:
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%x = uitofp i64 %a to double
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ret double %x
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; CHECK: @goou
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfidu 1, [[REG]]
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; CHECK: blr
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}
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