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a8a2b99aec
the default target of the first switch is not the basic block the second switch is in (PredDefault != BB). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163916 91177308-0d34-0410-b5e6-96231b3b80d8
141 lines
3.2 KiB
LLVM
141 lines
3.2 KiB
LLVM
; RUN: opt -simplifycfg -S -o - < %s | FileCheck %s
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declare void @func2(i32)
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declare void @func4(i32)
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declare void @func6(i32)
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declare void @func8(i32)
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;; test1 - create a switch with case 2 and case 4 from two branches: N == 2
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;; and N == 4.
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define void @test1(i32 %N) nounwind uwtable {
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entry:
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%cmp = icmp eq i32 %N, 2
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br i1 %cmp, label %if.then, label %if.else, !prof !0
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; CHECK: test1
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; CHECK: switch i32 %N
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; CHECK: ], !prof !0
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if.then:
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call void @func2(i32 %N) nounwind
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br label %if.end9
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if.else:
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%cmp2 = icmp eq i32 %N, 4
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br i1 %cmp2, label %if.then7, label %if.else8, !prof !1
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if.then7:
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call void @func4(i32 %N) nounwind
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br label %if.end
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if.else8:
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call void @func8(i32 %N) nounwind
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br label %if.end
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if.end:
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br label %if.end9
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if.end9:
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ret void
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}
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;; test2 - Merge two switches where PredDefault == BB.
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define void @test2(i32 %M, i32 %N) nounwind uwtable {
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entry:
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%cmp = icmp sgt i32 %M, 2
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br i1 %cmp, label %sw1, label %sw2
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sw1:
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switch i32 %N, label %sw2 [
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i32 2, label %sw.bb
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i32 3, label %sw.bb1
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], !prof !2
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; CHECK: test2
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; CHECK: switch i32 %N, label %sw.epilog
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; CHECK: i32 2, label %sw.bb
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; CHECK: i32 3, label %sw.bb1
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; CHECK: i32 4, label %sw.bb5
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; CHECK: ], !prof !1
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sw.bb:
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call void @func2(i32 %N) nounwind
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br label %sw.epilog
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sw.bb1:
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call void @func4(i32 %N) nounwind
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br label %sw.epilog
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sw2:
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;; Here "case 2" is invalidated if control is transferred through default case
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;; of the first switch.
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switch i32 %N, label %sw.epilog [
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i32 2, label %sw.bb4
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i32 4, label %sw.bb5
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], !prof !3
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sw.bb4:
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call void @func6(i32 %N) nounwind
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br label %sw.epilog
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sw.bb5:
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call void @func8(i32 %N) nounwind
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br label %sw.epilog
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sw.epilog:
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ret void
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}
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;; test3 - Merge two switches where PredDefault != BB.
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define void @test3(i32 %M, i32 %N) nounwind uwtable {
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entry:
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%cmp = icmp sgt i32 %M, 2
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br i1 %cmp, label %sw1, label %sw2
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sw1:
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switch i32 %N, label %sw.bb [
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i32 2, label %sw2
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i32 3, label %sw2
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i32 1, label %sw.bb1
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], !prof !4
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; CHECK: test3
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; CHECK: switch i32 %N, label %sw.bb
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; CHECK: i32 1, label %sw.bb1
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; CHECK: i32 3, label %sw.bb4
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; CHECK: i32 2, label %sw.epilog
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; CHECK: ], !prof !3
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sw.bb:
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call void @func2(i32 %N) nounwind
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br label %sw.epilog
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sw.bb1:
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call void @func4(i32 %N) nounwind
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br label %sw.epilog
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sw2:
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switch i32 %N, label %sw.epilog [
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i32 3, label %sw.bb4
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i32 4, label %sw.bb5
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], !prof !5
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sw.bb4:
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call void @func6(i32 %N) nounwind
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br label %sw.epilog
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sw.bb5:
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call void @func8(i32 %N) nounwind
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br label %sw.epilog
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sw.epilog:
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ret void
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}
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!0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
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!1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
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; CHECK: !0 = metadata !{metadata !"branch_weights", i32 256, i32 4352, i32 16}
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!2 = metadata !{metadata !"branch_weights", i32 4, i32 4, i32 8}
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!3 = metadata !{metadata !"branch_weights", i32 8, i32 8, i32 4}
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; CHECK: !1 = metadata !{metadata !"branch_weights", i32 32, i32 48, i32 96, i32 16}
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!4 = metadata !{metadata !"branch_weights", i32 7, i32 6, i32 4, i32 3}
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!5 = metadata !{metadata !"branch_weights", i32 17, i32 13, i32 9}
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; CHECK: !3 = metadata !{metadata !"branch_weights", i32 7, i32 3, i32 4, i32 6}
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