Tim Northover 630c5e06d6 AArch64: use RegisterOperand for NEON registers. ... Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-13 07:26:52 +00:00
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AArch64	AArch64: use RegisterOperand for NEON registers.	2013-09-13 07:26:52 +00:00
ARM	[ARMv8] Add some missing tests for DSB/DMB.	2013-09-05 16:05:45 +00:00
Mips	This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.	2013-09-06 13:08:00 +00:00
SystemZ	[SystemZ] Add TM and TMY	2013-09-10 10:20:32 +00:00
X86	Partial support for Intel SHA Extensions (sha1rnds4)	2013-09-12 15:51:31 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00