Andrew Lenharth eececbab32 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8

2005-12-25 17:36:48 +00:00

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.cvsignore

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Alpha.h

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Alpha.td

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AlphaAsmPrinter.cpp

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

AlphaCodeEmitter.cpp

massive DAGISel patch. lots and lots more stuff compiles now

2005-11-22 04:20:06 +00:00

AlphaInstrFormats.td

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

AlphaInstrInfo.cpp

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaInstrInfo.h

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AlphaInstrInfo.td

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

AlphaISelDAGToDAG.cpp

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

AlphaISelLowering.cpp

All that just to lower div and rem

2005-12-25 01:34:27 +00:00

AlphaISelLowering.h

All that just to lower div and rem

2005-12-25 01:34:27 +00:00

AlphaISelPattern.cpp

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

AlphaJITInfo.cpp

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AlphaJITInfo.h

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AlphaRegisterInfo.cpp

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaRegisterInfo.h

whatever. Intermediate patch to see what breaks. Seems ok.

2005-11-09 19:17:08 +00:00

AlphaRegisterInfo.td

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

AlphaRelocations.h

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AlphaSubtarget.cpp

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AlphaSubtarget.h

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AlphaTargetMachine.cpp

prevent latent switch creation

2005-11-18 13:57:03 +00:00

AlphaTargetMachine.h

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Makefile

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