mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f522068412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
768 lines
25 KiB
C++
768 lines
25 KiB
C++
//===-- PIC16ISelLowering.cpp - PIC16 DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PIC16 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pic16-lower"
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#include "PIC16ISelLowering.h"
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#include "PIC16TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode) {
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case PIC16ISD::Hi : return "PIC16ISD::Hi";
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case PIC16ISD::Lo : return "PIC16ISD::Lo";
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case PIC16ISD::Package : return "PIC16ISD::Package";
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case PIC16ISD::Wrapper : return "PIC16ISD::Wrapper";
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case PIC16ISD::SetBank : return "PIC16ISD::SetBank";
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case PIC16ISD::SetPage : return "PIC16ISD::SetPage";
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case PIC16ISD::Branch : return "PIC16ISD::Branch";
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case PIC16ISD::Cmp : return "PIC16ISD::Cmp";
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case PIC16ISD::BTFSS : return "PIC16ISD::BTFSS";
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case PIC16ISD::BTFSC : return "PIC16ISD::BTFSC";
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case PIC16ISD::XORCC : return "PIC16ISD::XORCC";
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case PIC16ISD::SUBCC : return "PIC16ISD::SUBCC";
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default : return NULL;
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}
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}
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PIC16TargetLowering::
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PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
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{
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// Set up the register classes.
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addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
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addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
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// Load extented operations for i1 types must be promoted .
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::ADD, MVT::i1, Promote);
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setOperationAction(ISD::ADD, MVT::i8, Legal);
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setOperationAction(ISD::ADD, MVT::i16, Custom);
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setOperationAction(ISD::ADD, MVT::i32, Expand);
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setOperationAction(ISD::ADD, MVT::i64, Expand);
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setOperationAction(ISD::SUB, MVT::i1, Promote);
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setOperationAction(ISD::SUB, MVT::i8, Legal);
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setOperationAction(ISD::SUB, MVT::i16, Custom);
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setOperationAction(ISD::SUB, MVT::i32, Expand);
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setOperationAction(ISD::SUB, MVT::i64, Expand);
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setOperationAction(ISD::ADDC, MVT::i1, Promote);
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setOperationAction(ISD::ADDC, MVT::i8, Legal);
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setOperationAction(ISD::ADDC, MVT::i16, Custom);
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setOperationAction(ISD::ADDC, MVT::i32, Expand);
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setOperationAction(ISD::ADDC, MVT::i64, Expand);
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setOperationAction(ISD::ADDE, MVT::i1, Promote);
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setOperationAction(ISD::ADDE, MVT::i8, Legal);
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setOperationAction(ISD::ADDE, MVT::i16, Custom);
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setOperationAction(ISD::ADDE, MVT::i32, Expand);
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setOperationAction(ISD::ADDE, MVT::i64, Expand);
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setOperationAction(ISD::SUBC, MVT::i1, Promote);
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setOperationAction(ISD::SUBC, MVT::i8, Legal);
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setOperationAction(ISD::SUBC, MVT::i16, Custom);
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setOperationAction(ISD::SUBC, MVT::i32, Expand);
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setOperationAction(ISD::SUBC, MVT::i64, Expand);
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setOperationAction(ISD::SUBE, MVT::i1, Promote);
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setOperationAction(ISD::SUBE, MVT::i8, Legal);
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setOperationAction(ISD::SUBE, MVT::i16, Custom);
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setOperationAction(ISD::SUBE, MVT::i32, Expand);
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setOperationAction(ISD::SUBE, MVT::i64, Expand);
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// PIC16 does not have these NodeTypes below.
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setOperationAction(ISD::SETCC, MVT::i1, Expand);
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setOperationAction(ISD::SETCC, MVT::i8, Expand);
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setOperationAction(ISD::SETCC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i1, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
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setOperationAction(ISD::BRCOND, MVT::i1, Expand);
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setOperationAction(ISD::BRCOND, MVT::i8, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i1, Custom);
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setOperationAction(ISD::BR_CC, MVT::i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// FIXME: Do we really need to Custom lower the GA ??
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setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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// Use the default for now.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::LOAD, MVT::i1, Promote);
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setOperationAction(ISD::LOAD, MVT::i8, Legal);
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setTargetDAGCombine(ISD::LOAD);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ADDE);
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setTargetDAGCombine(ISD::ADDC);
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::SUBE);
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setTargetDAGCombine(ISD::SUBC);
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setTargetDAGCombine(ISD::SUB);
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setStackPointerRegisterToSaveRestore(PIC16::STKPTR);
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computeRegisterProperties();
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}
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SDValue PIC16TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG)
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{
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SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
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switch (Op.getOpcode()) {
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case ISD::STORE:
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DOUT << "reduce store\n";
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break;
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case ISD::FORMAL_ARGUMENTS:
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DOUT << "==== lowering formal args\n";
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return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::GlobalAddress:
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DOUT << "==== lowering GA\n";
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return LowerGlobalAddress(Op, DAG);
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case ISD::RET:
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DOUT << "==== lowering ret\n";
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return LowerRET(Op, DAG);
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case ISD::FrameIndex:
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DOUT << "==== lowering frame index\n";
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return LowerFrameIndex(Op, DAG);
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case ISD::ADDE:
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DOUT << "==== lowering adde\n";
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break;
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case ISD::LOAD:
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case ISD::ADD:
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break;
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case ISD::BR_CC:
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DOUT << "==== lowering BR_CC\n";
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return LowerBR_CC(Op, DAG);
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} // end switch.
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return SDValue();
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}
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//===----------------------------------------------------------------------===//
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// Lower helper functions
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//===----------------------------------------------------------------------===//
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SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG)
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{
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MVT VT = Op.getValueType();
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue JumpVal = Op.getOperand(4);
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SDValue Result;
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unsigned cmpOpcode;
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unsigned branchOpcode;
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SDValue branchOperand;
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SDValue StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
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SDValue CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
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switch(CC) {
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default:
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assert(0 && "This condition code is not handled yet!!");
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abort();
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case ISD::SETNE:
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DOUT << "setne\n";
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cmpOpcode = PIC16ISD::XORCC;
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branchOpcode = PIC16ISD::BTFSS;
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branchOperand = DAG.getConstant(2, MVT::i8);
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break;
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case ISD::SETEQ:
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DOUT << "seteq\n";
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cmpOpcode = PIC16ISD::XORCC;
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branchOpcode = PIC16ISD::BTFSC;
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branchOperand = DAG.getConstant(2, MVT::i8);
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break;
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case ISD::SETGT:
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assert(0 && "Greater Than condition code is not handled yet!!");
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abort();
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break;
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case ISD::SETGE:
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DOUT << "setge\n";
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cmpOpcode = PIC16ISD::SUBCC;
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branchOpcode = PIC16ISD::BTFSS;
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branchOperand = DAG.getConstant(1, MVT::i8);
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break;
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case ISD::SETLT:
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DOUT << "setlt\n";
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cmpOpcode = PIC16ISD::SUBCC;
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branchOpcode = PIC16ISD::BTFSC;
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branchOperand = DAG.getConstant(1,MVT::i8);
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break;
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case ISD::SETLE:
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assert(0 && "Less Than Equal condition code is not handled yet!!");
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abort();
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break;
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} // End of Switch
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SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
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SDValue CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
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Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
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StatusReg, CmpValue);
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return Result;
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}
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//===----------------------------------------------------------------------===//
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// Misc Lower Operation implementation
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//===----------------------------------------------------------------------===//
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// LowerGlobalAddress - Create a constant pool entry for global value
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// and wrap it in a wrapper node.
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SDValue
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PIC16TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
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{
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MVT PtrVT = getPointerTy();
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GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
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GlobalValue *GV = GSDN->getGlobal();
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// FIXME: for now only do the ram.
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SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
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SDValue CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
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CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
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return CPAddr;
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}
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SDValue
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PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG)
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{
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switch(Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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return SDValue(); // ret void is legal
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}
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}
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SDValue
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PIC16TargetLowering::LowerFrameIndex(SDValue N, SelectionDAG &DAG)
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{
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
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return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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}
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return N;
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}
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SDValue
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PIC16TargetLowering::LowerLOAD(SDNode *N,
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SelectionDAG &DAG,
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DAGCombinerInfo &DCI) const
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{
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SDValue Outs[2];
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SDValue TF; //TokenFactor
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SDValue OutChains[2];
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SDValue Chain = N->getOperand(0);
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SDValue Src = N->getOperand(1);
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SDValue retVal;
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SDVTList VTList;
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// If this load is directly stored, replace the load value with the stored
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// value.
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// FIXME: Handle store large -> read small portion.
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// FIXME: Handle TRUNCSTORE/LOADEXT
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LoadSDNode *LD = cast<LoadSDNode>(N);
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SDValue Ptr = LD->getBasePtr();
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if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
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if (ISD::isNON_TRUNCStore(Chain.getNode())) {
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StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
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if (PrevST->getBasePtr() == Ptr &&
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PrevST->getValue().getValueType() == N->getValueType(0))
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return DCI.CombineTo(N, Chain.getOperand(1), Chain);
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}
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}
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if (N->getValueType(0) != MVT::i16)
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return SDValue();
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SDValue toWorklist;
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Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0);
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toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
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DAG.getConstant(1, MVT::i16));
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Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
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// FIXME: Add to worklist may not be needed.
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// It is meant to merge sequences of add with constant into one.
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DCI.AddToWorklist(toWorklist.getNode());
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// Create the tokenfactors and carry it on to the build_pair node
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OutChains[0] = Outs[0].getValue(1);
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OutChains[1] = Outs[1].getValue(1);
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TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &OutChains[0], 2);
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VTList = DAG.getVTList(MVT::i16, MVT::Flag);
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retVal = DAG.getNode (PIC16ISD::Package, VTList, &Outs[0], 2);
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DCI.CombineTo (N, retVal, TF);
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return retVal;
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}
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SDValue
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PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
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DAGCombinerInfo &DCI) const
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{
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bool changed = false;
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int i;
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SDValue LoOps[3], HiOps[3];
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SDValue OutOps[3]; // [0]:left, [1]:right, [2]:carry
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SDValue InOp[2];
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SDValue retVal;
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SDValue as1,as2;
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SDVTList VTList;
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unsigned AS = 0, ASE = 0, ASC=0;
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InOp[0] = N->getOperand(0);
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InOp[1] = N->getOperand(1);
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switch (N->getOpcode()) {
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case ISD::ADD:
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if (InOp[0].getOpcode() == ISD::Constant &&
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InOp[1].getOpcode() == ISD::Constant) {
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ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
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ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
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return DAG.getConstant(CST0->getZExtValue() + CST1->getZExtValue(),
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MVT::i16);
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}
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break;
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case ISD::ADDE:
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case ISD::ADDC:
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AS = ISD::ADD;
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ASE = ISD::ADDE;
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ASC = ISD::ADDC;
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break;
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case ISD::SUB:
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if (InOp[0].getOpcode() == ISD::Constant &&
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InOp[1].getOpcode() == ISD::Constant) {
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ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
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ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
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return DAG.getConstant(CST0->getZExtValue() - CST1->getZExtValue(),
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MVT::i16);
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}
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break;
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case ISD::SUBE:
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case ISD::SUBC:
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AS = ISD::SUB;
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ASE = ISD::SUBE;
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ASC = ISD::SUBC;
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break;
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} // end switch.
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assert ((N->getValueType(0) == MVT::i16)
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&& "expecting an MVT::i16 node for lowering");
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assert ((N->getOperand(0).getValueType() == MVT::i16)
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&& (N->getOperand(1).getValueType() == MVT::i16)
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&& "both inputs to addx/subx:i16 must be i16");
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for (i = 0; i < 2; i++) {
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if (InOp[i].getOpcode() == ISD::GlobalAddress) {
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// We don't want to lower subs/adds with global address yet.
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return SDValue();
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}
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else if (InOp[i].getOpcode() == ISD::Constant) {
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changed = true;
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ConstantSDNode *CST = dyn_cast<ConstantSDNode>(InOp[i]);
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LoOps[i] = DAG.getConstant(CST->getZExtValue() & 0xFF, MVT::i8);
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HiOps[i] = DAG.getConstant(CST->getZExtValue() >> 8, MVT::i8);
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}
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else if (InOp[i].getOpcode() == PIC16ISD::Package) {
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LoOps[i] = InOp[i].getOperand(0);
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HiOps[i] = InOp[i].getOperand(1);
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}
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else if (InOp[i].getOpcode() == ISD::LOAD) {
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changed = true;
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// LowerLOAD returns a Package node or it may combine and return
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// anything else.
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SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
|
|
|
|
// So If LowerLOAD returns something other than Package,
|
|
// then just call ADD again.
|
|
if (lowered.getOpcode() != PIC16ISD::Package)
|
|
return LowerADDSUB(N, DAG, DCI);
|
|
|
|
LoOps[i] = lowered.getOperand(0);
|
|
HiOps[i] = lowered.getOperand(1);
|
|
}
|
|
else if ((InOp[i].getOpcode() == ISD::ADD) ||
|
|
(InOp[i].getOpcode() == ISD::ADDE) ||
|
|
(InOp[i].getOpcode() == ISD::ADDC) ||
|
|
(InOp[i].getOpcode() == ISD::SUB) ||
|
|
(InOp[i].getOpcode() == ISD::SUBE) ||
|
|
(InOp[i].getOpcode() == ISD::SUBC)) {
|
|
changed = true;
|
|
// Must call LowerADDSUB recursively here,
|
|
// LowerADDSUB returns a Package node.
|
|
SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
|
|
|
|
LoOps[i] = lowered.getOperand(0);
|
|
HiOps[i] = lowered.getOperand(1);
|
|
}
|
|
else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) {
|
|
// FIXME: I am just zero extending. for now.
|
|
changed = true;
|
|
LoOps[i] = InOp[i].getOperand(0);
|
|
HiOps[i] = DAG.getConstant(0, MVT::i8);
|
|
}
|
|
else {
|
|
DAG.setGraphColor(N, "blue");
|
|
DAG.viewGraph();
|
|
assert (0 && "not implemented yet");
|
|
}
|
|
} // end for.
|
|
|
|
assert (changed && "nothing changed while lowering SUBx/ADDx");
|
|
|
|
VTList = DAG.getVTList(MVT::i8, MVT::Flag);
|
|
if (N->getOpcode() == ASE) {
|
|
// We must take in the existing carry
|
|
// if this node is part of an existing subx/addx sequence.
|
|
LoOps[2] = N->getOperand(2).getValue(1);
|
|
as1 = DAG.getNode (ASE, VTList, LoOps, 3);
|
|
}
|
|
else {
|
|
as1 = DAG.getNode (ASC, VTList, LoOps, 2);
|
|
}
|
|
HiOps[2] = as1.getValue(1);
|
|
as2 = DAG.getNode (ASE, VTList, HiOps, 3);
|
|
// We must build a pair that also provides the carry from sube/adde.
|
|
OutOps[0] = as1;
|
|
OutOps[1] = as2;
|
|
OutOps[2] = as2.getValue(1);
|
|
// Breaking an original i16, so lets make the Package also an i16.
|
|
if (N->getOpcode() == ASE) {
|
|
VTList = DAG.getVTList(MVT::i16, MVT::Flag);
|
|
retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3);
|
|
DCI.CombineTo (N, retVal, OutOps[2]);
|
|
}
|
|
else if (N->getOpcode() == ASC) {
|
|
VTList = DAG.getVTList(MVT::i16, MVT::Flag);
|
|
retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
|
|
DCI.CombineTo (N, retVal, OutOps[2]);
|
|
}
|
|
else if (N->getOpcode() == AS) {
|
|
VTList = DAG.getVTList(MVT::i16);
|
|
retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
|
|
DCI.CombineTo (N, retVal);
|
|
}
|
|
|
|
return retVal;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "PIC16GenCallingConv.inc"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CALL Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FORMAL_ARGUMENTS Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
SDValue PIC16TargetLowering::
|
|
LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
|
|
{
|
|
SmallVector<SDValue, 8> ArgValues;
|
|
SDValue Root = Op.getOperand(0);
|
|
|
|
// Return the new list of results.
|
|
// FIXME: Just copy right now.
|
|
ArgValues.push_back(Root);
|
|
|
|
return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
|
|
ArgValues.size()).getValue(Op.getResNo());
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Return Value Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// PIC16 Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target Optimization Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
|
|
DAGCombinerInfo &DCI) const
|
|
{
|
|
int i;
|
|
ConstantSDNode *CST;
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
break;
|
|
|
|
case PIC16ISD::Package:
|
|
DOUT << "==== combining PIC16ISD::Package\n";
|
|
return SDValue();
|
|
|
|
case ISD::ADD:
|
|
case ISD::SUB:
|
|
if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
|
|
(N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
|
|
// Do not touch pointer adds.
|
|
return SDValue ();
|
|
}
|
|
break;
|
|
|
|
case ISD::ADDE :
|
|
case ISD::ADDC :
|
|
case ISD::SUBE :
|
|
case ISD::SUBC :
|
|
if (N->getValueType(0) == MVT::i16) {
|
|
SDValue retVal = LowerADDSUB(N, DAG,DCI);
|
|
// LowerADDSUB has already combined the result,
|
|
// so we just return nothing to avoid assertion failure from llvm
|
|
// if N has been deleted already.
|
|
return SDValue();
|
|
}
|
|
else if (N->getValueType(0) == MVT::i8) {
|
|
// Sanity check ....
|
|
for (int i=0; i<2; i++) {
|
|
if (N->getOperand (i).getOpcode() == PIC16ISD::Package) {
|
|
assert (0 &&
|
|
"don't want to have PIC16ISD::Package as intput to add:i8");
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
// FIXME: split this large chunk of code.
|
|
case ISD::STORE :
|
|
{
|
|
SDValue Chain = N->getOperand(0);
|
|
SDValue Src = N->getOperand(1);
|
|
SDValue Dest = N->getOperand(2);
|
|
unsigned int DstOff = 0;
|
|
int NUM_STORES = 0;
|
|
SDValue Stores[6];
|
|
|
|
// if source operand is expected to be extended to
|
|
// some higher type then - remove this extension
|
|
// SDNode and do the extension manually
|
|
if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
|
|
(Src.getOpcode() == ISD::SIGN_EXTEND) ||
|
|
(Src.getOpcode() == ISD::ZERO_EXTEND)) {
|
|
Src = Src.getNode()->getOperand(0);
|
|
Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
|
|
return Stores[0];
|
|
}
|
|
|
|
switch(Src.getValueType().getSimpleVT()) {
|
|
default:
|
|
assert(false && "Invalid value type!");
|
|
|
|
case MVT::i8:
|
|
break;
|
|
|
|
case MVT::i16:
|
|
NUM_STORES = 2;
|
|
break;
|
|
|
|
case MVT::i32:
|
|
NUM_STORES = 4;
|
|
break;
|
|
|
|
case MVT::i64:
|
|
NUM_STORES = 8;
|
|
break;
|
|
}
|
|
|
|
if (isa<GlobalAddressSDNode>(Dest) && isa<LoadSDNode>(Src) &&
|
|
(Src.getValueType() != MVT::i8)) {
|
|
//create direct addressing a = b
|
|
Chain = Src.getOperand(0);
|
|
for (i=0; i<NUM_STORES; i++) {
|
|
SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
|
|
DAG.getConstant(DstOff, MVT::i16));
|
|
SDValue LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
|
|
SDValue DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
|
|
DAG.getConstant(DstOff, MVT::i16));
|
|
Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
|
|
Chain = Stores[i];
|
|
DstOff += 1;
|
|
}
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
|
|
return Chain;
|
|
}
|
|
else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src)
|
|
&& (Src.getValueType() != MVT::i8)) {
|
|
//create direct addressing a = CONST
|
|
CST = dyn_cast<ConstantSDNode>(Src);
|
|
for (i = 0; i < NUM_STORES; i++) {
|
|
SDValue CNST = DAG.getConstant(CST->getZExtValue() >> i*8, MVT::i8);
|
|
SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
|
|
DAG.getConstant(DstOff, MVT::i16));
|
|
Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
|
|
Chain = Stores[i];
|
|
DstOff += 1;
|
|
}
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
|
|
return Chain;
|
|
}
|
|
else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src)
|
|
&& (Src.getValueType() != MVT::i8)) {
|
|
// Create indirect addressing.
|
|
CST = dyn_cast<ConstantSDNode>(Src);
|
|
Chain = Dest.getOperand(0);
|
|
SDValue Load;
|
|
Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
|
|
Chain = Load.getValue(1);
|
|
for (i=0; i<NUM_STORES; i++) {
|
|
SDValue CNST = DAG.getConstant(CST->getZExtValue() >> i*8, MVT::i8);
|
|
Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
|
|
Chain = Stores[i];
|
|
DstOff += 1;
|
|
}
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
|
|
return Chain;
|
|
}
|
|
else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
|
|
// GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
|
|
return SDValue();
|
|
}
|
|
else if (Src.getOpcode() == PIC16ISD::Package) {
|
|
StoreSDNode *st = dyn_cast<StoreSDNode>(N);
|
|
SDValue toWorkList, retVal;
|
|
Chain = N->getOperand(0);
|
|
|
|
if (st->isTruncatingStore()) {
|
|
retVal = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
|
|
}
|
|
else {
|
|
toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
|
|
DAG.getConstant(1, MVT::i16));
|
|
Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
|
|
Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL,
|
|
0);
|
|
|
|
// We want to merge sequence of add with constant to one add and a
|
|
// constant, so add the ADD node to worklist to have llvm do that
|
|
// automatically.
|
|
DCI.AddToWorklist(toWorkList.getNode());
|
|
|
|
// We don't need the Package so add to worklist so llvm deletes it
|
|
DCI.AddToWorklist(Src.getNode());
|
|
retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
|
|
}
|
|
|
|
return retVal;
|
|
}
|
|
else if (Src.getOpcode() == ISD::TRUNCATE) {
|
|
}
|
|
else {
|
|
}
|
|
} // end ISD::STORE.
|
|
break;
|
|
|
|
case ISD::LOAD :
|
|
{
|
|
SDValue Ptr = N->getOperand(1);
|
|
if (Ptr.getOpcode() == PIC16ISD::Package) {
|
|
assert (0 && "not implemented yet");
|
|
}
|
|
}
|
|
break;
|
|
} // end switch.
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Utility functions
|
|
//===----------------------------------------------------------------------===//
|
|
const SDValue *PIC16TargetLowering::
|
|
findLoadi8(const SDValue &Src, SelectionDAG &DAG) const
|
|
{
|
|
unsigned int i;
|
|
if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
|
|
return &Src;
|
|
for (i=0; i<Src.getNumOperands(); i++) {
|
|
const SDValue *retVal = findLoadi8(Src.getOperand(i),DAG);
|
|
if (retVal) return retVal;
|
|
}
|
|
|
|
return NULL;
|
|
}
|