mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2b9355f2d9
64-bit SPARC v9 processes use biased stack and frame pointers, so the current function's stack frame is located at %sp+BIAS .. %fp+BIAS where BIAS = 2047. This makes more local variables directly accessible via [%fp+simm13] addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178965 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
4.0 KiB
LLVM
135 lines
4.0 KiB
LLVM
; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK: intarg
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; CHECK: stb %i0, [%i4]
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; CHECK: stb %i1, [%i4]
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; CHECK: sth %i2, [%i4]
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; CHECK: st %i3, [%i4]
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; CHECK: stx %i4, [%i4]
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; CHECK: st %i5, [%i4]
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; CHECK: ld [%fp+2227], [[R:%[gilo][0-7]]]
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; CHECK: st [[R]], [%i4]
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; CHECK: ldx [%fp+2231], [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%i4]
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define void @intarg(i8 %a0, ; %i0
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i8 %a1, ; %i1
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i16 %a2, ; %i2
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i32 %a3, ; %i3
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i8* %a4, ; %i4
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i32 %a5, ; %i5
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i32 %a6, ; [%fp+BIAS+176]
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i8* %a7) { ; [%fp+BIAS+184]
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store i8 %a0, i8* %a4
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store i8 %a1, i8* %a4
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%p16 = bitcast i8* %a4 to i16*
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store i16 %a2, i16* %p16
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%p32 = bitcast i8* %a4 to i32*
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store i32 %a3, i32* %p32
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%pp = bitcast i8* %a4 to i8**
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store i8* %a4, i8** %pp
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store i32 %a5, i32* %p32
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store i32 %a6, i32* %p32
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store i8* %a7, i8** %pp
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ret void
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}
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; CHECK: floatarg
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; CHECK: fstod %f1,
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; CHECK: faddd %f2,
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; CHECK: faddd %f4,
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; CHECK: faddd %f6,
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; CHECK: ld [%fp+2307], [[F:%f[0-9]+]]
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; CHECK: fadds %f31, [[F]]
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define double @floatarg(float %a0, ; %f1
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double %a1, ; %d2
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double %a2, ; %d4
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double %a3, ; %d6
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float %a4, ; %f9
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float %a5, ; %f11
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float %a6, ; %f13
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float %a7, ; %f15
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float %a8, ; %f17
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float %a9, ; %f19
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float %a10, ; %f21
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float %a11, ; %f23
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float %a12, ; %f25
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float %a13, ; %f27
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float %a14, ; %f29
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float %a15, ; %f31
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float %a16, ; [%fp+BIAS+256] (using 8 bytes)
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float %a17) { ; [%fp+BIAS+264] (using 8 bytes)
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%d0 = fpext float %a0 to double
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%s1 = fadd double %a1, %d0
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%s2 = fadd double %a2, %s1
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%s3 = fadd double %a3, %s2
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%s16 = fadd float %a15, %a16
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%d16 = fpext float %s16 to double
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%s17 = fadd double %d16, %s3
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ret double %s17
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}
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; CHECK: mixedarg
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; CHECK: fstod %f3
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; CHECK: faddd %f6
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; CHECK: faddd %f16
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; CHECK: ldx [%fp+2231]
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; CHECK: ldx [%fp+2247]
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define void @mixedarg(i8 %a0, ; %i0
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float %a1, ; %f3
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i16 %a2, ; %i2
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double %a3, ; %d6
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i13 %a4, ; %i4
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float %a5, ; %f11
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i64 %a6, ; [%fp+BIAS+176]
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double *%a7, ; [%fp+BIAS+184]
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double %a8, ; %d16
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i16* %a9) { ; [%fp+BIAS+200]
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%d1 = fpext float %a1 to double
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%s3 = fadd double %a3, %d1
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%s8 = fadd double %a8, %s3
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store double %s8, double* %a7
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store i16 %a2, i16* %a9
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ret void
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}
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; The inreg attribute is used to indicate 32-bit sized struct elements that
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; share an 8-byte slot.
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; CHECK: inreg_fi
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; CHECK: fstoi %f1
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; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
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; CHECK: sub [[R]],
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define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0
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float inreg %a1) { ; %f1
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%b1 = fptosi float %a1 to i32
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%rv = sub i32 %a0, %b1
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ret i32 %rv
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}
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; CHECK: inreg_ff
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; CHECK: fsubs %f0, %f1, %f1
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define float @inreg_ff(float inreg %a0, ; %f0
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float inreg %a1) { ; %f1
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%rv = fsub float %a0, %a1
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ret float %rv
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}
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; CHECK: inreg_if
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; CHECK: fstoi %f0
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; CHECK: sub %i0
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define i32 @inreg_if(float inreg %a0, ; %f0
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i32 inreg %a1) { ; low bits of %i0
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%b0 = fptosi float %a0 to i32
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%rv = sub i32 %a1, %b0
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ret i32 %rv
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}
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; The frontend shouldn't do this. Just pass i64 instead.
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; CHECK: inreg_ii
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; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
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; CHECK: sub %i0, [[R]], %i0
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define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
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i32 inreg %a1) { ; low bits of %i0
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%rv = sub i32 %a1, %a0
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ret i32 %rv
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}
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