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48575f6ea7
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.5 KiB
C++
54 lines
1.5 KiB
C++
//===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling ARM functions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMHAZARDRECOGNIZER_H
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#define ARMHAZARDRECOGNIZER_H
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#include "llvm/CodeGen/PostRAHazardRecognizer.h"
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namespace llvm {
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class ARMBaseInstrInfo;
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class ARMBaseRegisterInfo;
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class ARMSubtarget;
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class MachineInstr;
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class ARMHazardRecognizer : public PostRAHazardRecognizer {
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const ARMBaseInstrInfo &TII;
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const ARMBaseRegisterInfo &TRI;
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const ARMSubtarget &STI;
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MachineInstr *LastMI;
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unsigned Stalls;
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unsigned ITBlockSize; // No. of MIs in current IT block yet to be scheduled.
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MachineInstr *ITBlockMIs[4];
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public:
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ARMHazardRecognizer(const InstrItineraryData *ItinData,
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const ARMBaseInstrInfo &tii,
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const ARMBaseRegisterInfo &tri,
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const ARMSubtarget &sti) :
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PostRAHazardRecognizer(ItinData), TII(tii), TRI(tri), STI(sti),
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LastMI(0), ITBlockSize(0) {}
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virtual HazardType getHazardType(SUnit *SU);
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virtual void Reset();
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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};
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} // end namespace llvm
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#endif // ARMHAZARDRECOGNIZER_H
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