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https://github.com/c64scene-ar/llvm-6502.git
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2d81106fa0
Targets like SPARC and MIPS have delay slots and normally bundle the delay slot instruction with the corresponding terminator. Teach isBlockOnlyReachableByFallthrough to find any MBB operands on bundled terminators so SPARC doesn't need to specialize this function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199061 91177308-0d34-0410-b5e6-96231b3b80d8
395 lines
14 KiB
C++
395 lines
14 KiB
C++
//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format SPARC assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "Sparc.h"
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#include "InstPrinter/SparcInstPrinter.h"
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#include "MCTargetDesc/SparcBaseInfo.h"
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#include "MCTargetDesc/SparcMCExpr.h"
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#include "SparcInstrInfo.h"
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#include "SparcTargetMachine.h"
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#include "SparcTargetStreamer.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class SparcAsmPrinter : public AsmPrinter {
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SparcTargetStreamer &getTargetStreamer() {
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return static_cast<SparcTargetStreamer&>(OutStreamer.getTargetStreamer());
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}
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public:
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explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {}
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virtual const char *getPassName() const {
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return "Sparc Assembly Printer";
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}
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
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const char *Modifier = 0);
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void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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virtual void EmitFunctionBodyStart();
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virtual void EmitInstruction(const MachineInstr *MI);
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static const char *getRegisterName(unsigned RegNo) {
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return SparcInstPrinter::getRegisterName(RegNo);
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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};
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} // end of anonymous namespace
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static MCOperand createPCXCallOP(MCSymbol *Label,
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MCContext &OutContext)
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{
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Label,
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OutContext);
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const SparcMCExpr *expr = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_None,
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MCSym, OutContext);
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return MCOperand::CreateExpr(expr);
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}
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static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
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MCSymbol *GOTLabel, MCSymbol *StartLabel,
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MCSymbol *CurLabel,
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MCContext &OutContext)
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{
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const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext);
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const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel,
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OutContext);
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const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel,
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OutContext);
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const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext);
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const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
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const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
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Add, OutContext);
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return MCOperand::CreateExpr(expr);
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}
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static void EmitCall(MCStreamer &OutStreamer,
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MCOperand &Callee)
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{
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MCInst CallInst;
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CallInst.setOpcode(SP::CALL);
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CallInst.addOperand(Callee);
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OutStreamer.EmitInstruction(CallInst);
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}
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static void EmitSETHI(MCStreamer &OutStreamer,
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MCOperand &Imm, MCOperand &RD)
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{
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MCInst SETHIInst;
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SETHIInst.setOpcode(SP::SETHIi);
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SETHIInst.addOperand(RD);
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SETHIInst.addOperand(Imm);
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OutStreamer.EmitInstruction(SETHIInst);
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}
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static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1,
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MCOperand &Imm, MCOperand &RD)
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{
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MCInst ORInst;
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ORInst.setOpcode(SP::ORri);
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ORInst.addOperand(RD);
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ORInst.addOperand(RS1);
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ORInst.addOperand(Imm);
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OutStreamer.EmitInstruction(ORInst);
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}
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static void EmitADD(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &RS2, MCOperand &RD)
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{
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MCInst ADDInst;
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ADDInst.setOpcode(SP::ADDrr);
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ADDInst.addOperand(RD);
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ADDInst.addOperand(RS1);
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ADDInst.addOperand(RS2);
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OutStreamer.EmitInstruction(ADDInst);
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}
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static void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
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MCStreamer &OutStreamer,
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MCContext &OutContext)
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{
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const MachineOperand &MO = MI->getOperand(0);
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MCSymbol *StartLabel = OutContext.CreateTempSymbol();
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MCSymbol *EndLabel = OutContext.CreateTempSymbol();
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MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
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MCSymbol *GOTLabel =
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OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
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assert(MO.getReg() != SP::O7 &&
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"%o7 is assigned as destination for getpcx!");
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MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
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MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
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// <StartLabel>:
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// call <EndLabel>
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// <SethiLabel>:
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// sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
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// <EndLabel>:
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// or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
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// add <MO>, %o7, <MO>
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OutStreamer.EmitLabel(StartLabel);
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MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
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EmitCall(OutStreamer, Callee);
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OutStreamer.EmitLabel(SethiLabel);
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MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_HI,
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GOTLabel, StartLabel, SethiLabel,
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OutContext);
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EmitSETHI(OutStreamer, hiImm, MCRegOP);
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OutStreamer.EmitLabel(EndLabel);
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MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_LO,
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GOTLabel, StartLabel, EndLabel,
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OutContext);
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EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
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EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
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}
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void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
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{
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switch (MI->getOpcode()) {
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default: break;
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case TargetOpcode::DBG_VALUE:
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// FIXME: Debug Value.
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return;
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case SP::GETPCX:
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LowerGETPCXAndEmitMCInsts(MI, OutStreamer, OutContext);
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return;
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}
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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MCInst TmpInst;
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LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
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OutStreamer.EmitInstruction(TmpInst);
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check.
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}
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void SparcAsmPrinter::EmitFunctionBodyStart() {
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if (!TM.getSubtarget<SparcSubtarget>().is64Bit())
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return;
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
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for (unsigned i = 0; globalRegs[i] != 0; ++i) {
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unsigned reg = globalRegs[i];
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if (MRI.use_empty(reg))
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continue;
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if (reg == SP::G6 || reg == SP::G7)
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getTargetStreamer().emitSparcRegisterIgnore(reg);
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else
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getTargetStreamer().emitSparcRegisterScratch(reg);
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}
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}
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void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const DataLayout *DL = TM.getDataLayout();
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const MachineOperand &MO = MI->getOperand (opNum);
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unsigned TF = MO.getTargetFlags();
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#ifndef NDEBUG
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// Verify the target flags.
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if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
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if (MI->getOpcode() == SP::CALL)
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assert(TF == SPII::MO_NO_FLAG &&
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"Cannot handle target flags on call address");
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else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
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assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
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|| TF == SPII::MO_TLS_GD_HI22
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|| TF == SPII::MO_TLS_LDM_HI22
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|| TF == SPII::MO_TLS_LDO_HIX22
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|| TF == SPII::MO_TLS_IE_HI22
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|| TF == SPII::MO_TLS_LE_HIX22) &&
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"Invalid target flags for address operand on sethi");
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else if (MI->getOpcode() == SP::TLS_CALL)
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assert((TF == SPII::MO_NO_FLAG
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|| TF == SPII::MO_TLS_GD_CALL
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|| TF == SPII::MO_TLS_LDM_CALL) &&
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"Cannot handle target flags on tls call address");
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else if (MI->getOpcode() == SP::TLS_ADDrr)
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assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
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|| TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
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"Cannot handle target flags on add for TLS");
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else if (MI->getOpcode() == SP::TLS_LDrr)
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assert(TF == SPII::MO_TLS_IE_LD &&
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"Cannot handle target flags on ld for TLS");
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else if (MI->getOpcode() == SP::TLS_LDXrr)
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assert(TF == SPII::MO_TLS_IE_LDX &&
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"Cannot handle target flags on ldx for TLS");
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else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
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assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
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"Cannot handle target flags on xor for TLS");
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else
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assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
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|| TF == SPII::MO_HM
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|| TF == SPII::MO_TLS_GD_LO10
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|| TF == SPII::MO_TLS_LDM_LO10
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|| TF == SPII::MO_TLS_IE_LO10 ) &&
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"Invalid target flags for small address operand");
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}
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#endif
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bool CloseParen = true;
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switch (TF) {
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default:
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llvm_unreachable("Unknown target flags on operand");
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case SPII::MO_NO_FLAG:
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CloseParen = false;
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break;
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case SPII::MO_LO: O << "%lo("; break;
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case SPII::MO_HI: O << "%hi("; break;
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case SPII::MO_H44: O << "%h44("; break;
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case SPII::MO_M44: O << "%m44("; break;
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case SPII::MO_L44: O << "%l44("; break;
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case SPII::MO_HH: O << "%hh("; break;
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case SPII::MO_HM: O << "%hm("; break;
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case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
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case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
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case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
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case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
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case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
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case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
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case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
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case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
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case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
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case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
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case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
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case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
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case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
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case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
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case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
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case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
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case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
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case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
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}
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
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break;
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case MachineOperand::MO_Immediate:
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O << (int)MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_GlobalAddress:
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O << *getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress:
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O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
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break;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << DL->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
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<< MO.getIndex();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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if (CloseParen) O << ")";
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}
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void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O, const char *Modifier) {
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printOperand(MI, opNum, O);
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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O << ", ";
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printOperand(MI, opNum+1, O);
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return;
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}
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if (MI->getOperand(opNum+1).isReg() &&
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MI->getOperand(opNum+1).getReg() == SP::G0)
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return; // don't print "+%g0"
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if (MI->getOperand(opNum+1).isImm() &&
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MI->getOperand(opNum+1).getImm() == 0)
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return; // don't print "+0"
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O << "+";
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printOperand(MI, opNum+1, O);
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
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///
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bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default:
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// See if this is a generic print operand
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return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
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case 'r':
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break;
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}
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}
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printOperand(MI, OpNo, O);
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return false;
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}
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bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier
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O << '[';
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printMemOperand(MI, OpNo, O);
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O << ']';
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return false;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeSparcAsmPrinter() {
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RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
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RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);
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}
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