Daniel Sanders 144749b59b Merging r227430: ...

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r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235864 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-27 11:59:49 +00:00

..

AArch64

Update AArch64 ELF relocations to ABI 1.0

2014-11-26 10:49:18 +00:00

ARM

Merging r227603:

2015-02-02 20:45:12 +00:00

AsmParser

MC: Don't emit .no_dead_strip on targets which don't support it

2014-12-24 04:11:42 +00:00

COFF

Merging r228565:

2015-02-10 03:52:36 +00:00

Disassembler

Merging r227430:

2015-04-27 11:59:49 +00:00

ELF

Merging r229911 by d0k:

2015-03-09 18:07:19 +00:00

Hexagon

[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.

2014-12-09 18:16:49 +00:00

MachO

Port r226022 to the 3.6 branch.

2015-01-17 00:38:54 +00:00

Markup

…

Mips

Merging r226905:

2015-04-27 09:44:39 +00:00

PowerPC

[PowerPC] Add support for the CMPB instruction

2015-01-03 01:16:37 +00:00

R600

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

Sparc

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

SystemZ

Exclude known and bugzilled failures from UBSan bootstrap

2014-09-17 20:17:52 +00:00

X86

X86: validate 'int' instruction

2015-01-14 05:10:21 +00:00