Kevin Qin 2daff76c05 [AArch64] Fix a bug generating incorrect instruction when building small vector. ... This bug is introduced by r211144. The element of operand may be smaller than the element of result, but previous commit can only handle the contrary condition. This commit is to handle this scenario and generate optimized codes like ZIP1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213830 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-24 02:05:42 +00:00
..
Analysis	Make use of the align parameter attribute for all pointer arguments	2014-07-22 16:58:55 +00:00
AsmParser	AsmParser: remove deprecated LLIR support	2014-07-23 18:09:31 +00:00
Bitcode	Add a dereferenceable attribute	2014-07-18 15:51:28 +00:00
CodeGen	Fix indenting.	2014-07-23 22:34:13 +00:00
DebugInfo	Revert "Introduce a string_ostream string builder facilty"	2014-06-26 22:52:05 +00:00
ExecutionEngine	ExecutionEngine: remove a stray semicolon	2014-07-23 18:09:28 +00:00
IR	Rename metadata llvm.loop.vectorize.unroll to llvm.loop.vectorize.interleave.	2014-07-21 23:11:03 +00:00
IRReader	Update the MemoryBuffer API to use ErrorOr.	2014-07-06 17:43:13 +00:00
LineEditor
Linker	Include <tuple> to make buildbots happy	2014-06-27 18:38:12 +00:00
LTO	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
MC	Finish inverting the MC -> Object dependency.	2014-07-23 22:26:07 +00:00
Object	AArch64: remove arm64 triple enumerator.	2014-07-23 12:32:47 +00:00
Option	Generic: add range-adapter for option parsing.	2014-07-09 13:03:37 +00:00
ProfileData	Update the MemoryBuffer API to use ErrorOr.	2014-07-06 17:43:13 +00:00
Support	AArch64: remove "arm64_be" support in favour of "aarch64_be".	2014-07-23 12:58:11 +00:00
TableGen	[TableGen] Allow shift operators to take bits<n>	2014-07-17 17:04:27 +00:00
Target	[AArch64] Fix a bug generating incorrect instruction when building small vector.	2014-07-24 02:05:42 +00:00
Transforms	SimplifyCFG: fix a bug in switch to table conversion	2014-07-23 23:13:23 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile