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Not functionality change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
574 lines
20 KiB
C++
574 lines
20 KiB
C++
//===-- SelectionDAGBuild.h - Selection-DAG building ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SELECTIONDAGBUILD_H
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#define SELECTIONDAGBUILD_H
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SmallSet.h"
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#endif
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <vector>
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#include <set>
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namespace llvm {
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class AliasAnalysis;
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class AllocaInst;
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class BasicBlock;
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class BitCastInst;
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class BranchInst;
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class CallInst;
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class ExtractElementInst;
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class ExtractValueInst;
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class FCmpInst;
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class FPExtInst;
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class FPToSIInst;
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class FPToUIInst;
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class FPTruncInst;
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class FreeInst;
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class Function;
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class GetElementPtrInst;
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class GCFunctionInfo;
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class ICmpInst;
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class IntToPtrInst;
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class InvokeInst;
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class InsertElementInst;
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class InsertValueInst;
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class Instruction;
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class LoadInst;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineModuleInfo;
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class MachineRegisterInfo;
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class MallocInst;
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class PHINode;
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class PtrToIntInst;
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class ReturnInst;
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class SDISelAsmOperandInfo;
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class SExtInst;
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class SelectInst;
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class ShuffleVectorInst;
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class SIToFPInst;
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class StoreInst;
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class SwitchInst;
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class TargetData;
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class TargetLowering;
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class TruncInst;
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class UIToFPInst;
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class UnreachableInst;
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class UnwindInst;
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class VAArgInst;
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class ZExtInst;
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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///
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class FunctionLoweringInfo {
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public:
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TargetLowering &TLI;
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Function *Fn;
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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explicit FunctionLoweringInfo(TargetLowering &TLI);
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/// set - Initialize this FunctionLoweringInfo with the given Function
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/// and its associated MachineFunction.
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///
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void set(Function &Fn, MachineFunction &MF, SelectionDAG &DAG,
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bool EnableFastISel);
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/// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
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DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
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/// ValueMap - Since we emit code for the function a basic block at a time,
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/// we must remember which virtual registers hold the values for
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/// cross-basic-block values.
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DenseMap<const Value*, unsigned> ValueMap;
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/// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
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/// the entry block. This allows the allocas to be efficiently referenced
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/// anywhere in the function.
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DenseMap<const AllocaInst*, int> StaticAllocaMap;
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#ifndef NDEBUG
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SmallSet<Instruction*, 8> CatchInfoLost;
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SmallSet<Instruction*, 8> CatchInfoFound;
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#endif
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unsigned MakeReg(EVT VT);
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/// isExportedInst - Return true if the specified value is an instruction
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/// exported from its block.
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bool isExportedInst(const Value *V) {
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return ValueMap.count(V);
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}
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unsigned CreateRegForValue(const Value *V);
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unsigned InitializeRegForValue(const Value *V) {
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unsigned &R = ValueMap[V];
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assert(R == 0 && "Already initialized this value register!");
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return R = CreateRegForValue(V);
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}
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struct LiveOutInfo {
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unsigned NumSignBits;
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APInt KnownOne, KnownZero;
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LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
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};
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/// LiveOutRegInfo - Information about live out vregs, indexed by their
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/// register number offset by 'FirstVirtualRegister'.
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std::vector<LiveOutInfo> LiveOutRegInfo;
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/// clear - Clear out all the function-specific state. This returns this
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/// FunctionLoweringInfo to an empty state, ready to be used for a
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/// different function.
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void clear() {
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MBBMap.clear();
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ValueMap.clear();
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StaticAllocaMap.clear();
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#ifndef NDEBUG
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CatchInfoLost.clear();
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CatchInfoFound.clear();
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#endif
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LiveOutRegInfo.clear();
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}
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};
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//===----------------------------------------------------------------------===//
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/// SelectionDAGLowering - This is the common target-independent lowering
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/// implementation that is parameterized by a TargetLowering object.
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/// Also, targets can overload any lowering method.
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///
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class SelectionDAGLowering {
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MachineBasicBlock *CurMBB;
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/// CurDebugLoc - current file + line number. Changes as we build the DAG.
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DebugLoc CurDebugLoc;
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DenseMap<const Value*, SDValue> NodeMap;
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/// PendingLoads - Loads are not emitted to the program immediately. We bunch
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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SmallVector<SDValue, 8> PendingLoads;
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// instruction, but they have no other ordering requirements. We bunch them
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/// up and the emit a single tokenfactor for them just before terminator
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/// instructions.
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SmallVector<SDValue, 8> PendingExports;
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/// Case - A struct to record the Value for a switch case, and the
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/// case's target basic block.
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struct Case {
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Constant* Low;
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Constant* High;
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MachineBasicBlock* BB;
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Case() : Low(0), High(0), BB(0) { }
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Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
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Low(low), High(high), BB(bb) { }
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uint64_t size() const {
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uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
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uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
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return (rHigh - rLow + 1ULL);
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}
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};
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struct CaseBits {
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uint64_t Mask;
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MachineBasicBlock* BB;
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unsigned Bits;
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CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
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Mask(mask), BB(bb), Bits(bits) { }
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};
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typedef std::vector<Case> CaseVector;
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typedef std::vector<CaseBits> CaseBitsVector;
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typedef CaseVector::iterator CaseItr;
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typedef std::pair<CaseItr, CaseItr> CaseRange;
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/// CaseRec - A struct with ctor used in lowering switches to a binary tree
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/// of conditional branches.
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struct CaseRec {
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CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
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CaseBB(bb), LT(lt), GE(ge), Range(r) {}
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/// CaseBB - The MBB in which to emit the compare and branch
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MachineBasicBlock *CaseBB;
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/// LT, GE - If nonzero, we know the current case value must be less-than or
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/// greater-than-or-equal-to these Constants.
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Constant *LT;
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Constant *GE;
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/// Range - A pair of iterators representing the range of case values to be
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/// processed at this point in the binary search tree.
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CaseRange Range;
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};
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typedef std::vector<CaseRec> CaseRecVector;
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/// The comparison function for sorting the switch case values in the vector.
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/// WARNING: Case ranges should be disjoint!
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struct CaseCmp {
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bool operator () (const Case& C1, const Case& C2) {
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assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
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const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
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const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
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return CI1->getValue().slt(CI2->getValue());
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}
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};
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struct CaseBitsCmp {
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bool operator () (const CaseBits& C1, const CaseBits& C2) {
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return C1.Bits > C2.Bits;
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}
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};
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size_t Clusterify(CaseVector& Cases, const SwitchInst &SI);
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/// CaseBlock - This structure is used to communicate between SDLowering and
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(APInt F, APInt L, Value* SV, MachineBasicBlock* H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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APInt First;
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APInt Last;
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Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
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Mask(M), ThisBB(T), TargetBB(Tr) { }
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uint64_t Mask;
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MachineBasicBlock* ThisBB;
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MachineBasicBlock* TargetBB;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(APInt F, APInt R, Value* SV,
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unsigned Rg, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
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Parent(P), Default(D), Cases(C) { }
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APInt First;
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APInt Range;
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Value *SValue;
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unsigned Reg;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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public:
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// TLI - This is information that describes the available target features we
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// need for lowering. This indicates when operations are unavailable,
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// implemented with a libcall, etc.
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TargetLowering &TLI;
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SelectionDAG &DAG;
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const TargetData *TD;
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AliasAnalysis *AA;
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<CaseBlock> SwitchCases;
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/// JTCases - Vector of JumpTable structures used to communicate
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/// SwitchInst code generation information.
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std::vector<JumpTableBlock> JTCases;
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/// BitTestCases - Vector of BitTestBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<BitTestBlock> BitTestCases;
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/// PHINodesToUpdate - A list of phi instructions whose operand list will
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/// be updated after processing the current basic block.
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std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
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/// EdgeMapping - If an edge from CurMBB to any MBB is changed (e.g. due to
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/// scheduler custom lowering), track the change here.
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> EdgeMapping;
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// Emit PHI-node-operand constants only once even if used by multiple
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// PHI nodes.
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DenseMap<Constant*, unsigned> ConstantsOut;
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/// FuncInfo - Information about the function as a whole.
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///
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FunctionLoweringInfo &FuncInfo;
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/// OptLevel - What optimization level we're generating code for.
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///
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CodeGenOpt::Level OptLevel;
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/// GFI - Garbage collection metadata for the function.
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GCFunctionInfo *GFI;
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/// HasTailCall - This is set to true if a call in the current
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/// block has been translated as a tail call. In this case,
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/// no subsequent DAG nodes should be created.
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///
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bool HasTailCall;
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LLVMContext *Context;
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SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
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FunctionLoweringInfo &funcinfo,
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CodeGenOpt::Level ol)
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: CurDebugLoc(DebugLoc::getUnknownLoc()),
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TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
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HasTailCall(false),
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Context(dag.getContext()) {
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}
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void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
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/// clear - Clear out the curret SelectionDAG and the associated
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/// state and prepare this SelectionDAGLowering object to be used
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/// for a new block. This doesn't clear out information about
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/// additional blocks that are needed to complete switch lowering
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/// or PHI node updating; that information is cleared out as it is
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/// consumed.
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void clear();
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/// getRoot - Return the current virtual root of the Selection DAG,
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/// flushing any PendingLoad items. This must be done before emitting
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/// a store or any other node that may need to be ordered after any
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/// prior load instructions.
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///
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SDValue getRoot();
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/// getControlRoot - Similar to getRoot, but instead of flushing all the
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/// PendingLoad items, flush all the PendingExports items. It is necessary
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/// to do this before emitting a terminator instruction.
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///
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SDValue getControlRoot();
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DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
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void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; }
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void CopyValueToVirtualRegister(Value *V, unsigned Reg);
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void visit(Instruction &I);
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void visit(unsigned Opcode, User &I);
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void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
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SDValue getValue(const Value *V);
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void setValue(const Value *V, SDValue NewN) {
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SDValue &N = NodeMap[V];
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assert(N.getNode() == 0 && "Already set a value for this node!");
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N = NewN;
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}
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void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs);
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void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
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unsigned Opc);
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void EmitBranchForMergedCondition(Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB);
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bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
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bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
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void CopyToExportRegsIfNeeded(Value *V);
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void ExportFromCurrentBlock(Value *V);
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void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
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MachineBasicBlock *LandingPad = NULL);
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private:
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// Terminator instructions.
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void visitRet(ReturnInst &I);
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void visitBr(BranchInst &I);
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void visitSwitch(SwitchInst &I);
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void visitUnreachable(UnreachableInst &I) { /* noop */ }
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// Helpers for visitSwitch
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bool handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default);
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bool handleJTSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default);
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bool handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default);
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bool handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default);
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public:
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void visitSwitchCase(CaseBlock &CB);
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void visitBitTestHeader(BitTestBlock &B);
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void visitBitTestCase(MachineBasicBlock* NextMBB,
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unsigned Reg,
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BitTestCase &B);
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void visitJumpTable(JumpTable &JT);
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void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
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private:
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// These all get lowered before this pass.
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void visitInvoke(InvokeInst &I);
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void visitUnwind(UnwindInst &I);
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void visitBinary(User &I, unsigned OpCode);
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void visitShift(User &I, unsigned Opcode);
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void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
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void visitFAdd(User &I) { visitBinary(I, ISD::FADD); }
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void visitSub(User &I) { visitBinary(I, ISD::SUB); }
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void visitFSub(User &I);
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void visitMul(User &I) { visitBinary(I, ISD::MUL); }
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void visitFMul(User &I) { visitBinary(I, ISD::FMUL); }
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void visitURem(User &I) { visitBinary(I, ISD::UREM); }
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void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
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void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
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void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
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void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
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void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
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void visitAnd (User &I) { visitBinary(I, ISD::AND); }
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void visitOr (User &I) { visitBinary(I, ISD::OR); }
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void visitXor (User &I) { visitBinary(I, ISD::XOR); }
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void visitShl (User &I) { visitShift(I, ISD::SHL); }
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void visitLShr(User &I) { visitShift(I, ISD::SRL); }
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void visitAShr(User &I) { visitShift(I, ISD::SRA); }
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void visitICmp(User &I);
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void visitFCmp(User &I);
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// Visit the conversion instructions
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|
void visitTrunc(User &I);
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|
void visitZExt(User &I);
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void visitSExt(User &I);
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void visitFPTrunc(User &I);
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void visitFPExt(User &I);
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void visitFPToUI(User &I);
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void visitFPToSI(User &I);
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void visitUIToFP(User &I);
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|
void visitSIToFP(User &I);
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|
void visitPtrToInt(User &I);
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|
void visitIntToPtr(User &I);
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|
void visitBitCast(User &I);
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|
|
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void visitExtractElement(User &I);
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|
void visitInsertElement(User &I);
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|
void visitShuffleVector(User &I);
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|
|
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void visitExtractValue(ExtractValueInst &I);
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|
void visitInsertValue(InsertValueInst &I);
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|
|
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void visitGetElementPtr(User &I);
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|
void visitSelect(User &I);
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|
|
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void visitMalloc(MallocInst &I);
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|
void visitFree(FreeInst &I);
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|
void visitAlloca(AllocaInst &I);
|
|
void visitLoad(LoadInst &I);
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|
void visitStore(StoreInst &I);
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void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
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|
void visitCall(CallInst &I);
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|
void visitInlineAsm(CallSite CS);
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|
const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
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void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
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|
|
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void visitPow(CallInst &I);
|
|
void visitExp2(CallInst &I);
|
|
void visitExp(CallInst &I);
|
|
void visitLog(CallInst &I);
|
|
void visitLog2(CallInst &I);
|
|
void visitLog10(CallInst &I);
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|
|
|
void visitVAStart(CallInst &I);
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|
void visitVAArg(VAArgInst &I);
|
|
void visitVAEnd(CallInst &I);
|
|
void visitVACopy(CallInst &I);
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|
|
|
void visitUserOp1(Instruction &I) {
|
|
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
|
|
}
|
|
void visitUserOp2(Instruction &I) {
|
|
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
|
|
}
|
|
|
|
const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
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|
const char *implVisitAluOverflow(CallInst &I, ISD::NodeType Op);
|
|
};
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|
|
|
/// AddCatchInfo - Extract the personality and type infos from an eh.selector
|
|
/// call, and add them to the specified machine basic block.
|
|
void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
|
|
MachineBasicBlock *MBB);
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|
|
|
} // end namespace llvm
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#endif
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