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https://github.com/c64scene-ar/llvm-6502.git
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e4439438f6
This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206398 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.7 KiB
ArmAsm
95 lines
2.7 KiB
ArmAsm
# Instructions that are valid
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#
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# FIXME: Test MIPS-I instead of MIPS32
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
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.set noat
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abs.d $f7,$f25 # CHECK: encoding:
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abs.s $f9,$f16
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add $s7,$s2,$a1
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add.d $f1,$f7,$f29
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add.s $f8,$f21,$f24
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addi $t5,$t1,26322
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addu $t1,$a0,$a2
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and $s7,$v0,$t4
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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c.sf.s $f14,$f22
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cfc1 $s1,$21
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ctc1 $a2,$26
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cvt.d.s $f22,$f28
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cvt.d.w $f26,$f11
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cvt.s.d $f26,$f8
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cvt.s.w $f22,$f15
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cvt.w.d $f20,$f14
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cvt.w.s $f20,$f24
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div $zero,$t9,$t3
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div.d $f29,$f20,$f27
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div.s $f4,$f5,$f15
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divu $zero,$t9,$t7
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ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
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lb $t8,-14515($t2)
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lbu $t0,30195($v1)
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lh $t3,-8556($s5)
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lhu $s3,-22851($v0)
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li $at,-29773
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li $zero,-29889
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lw $t0,5674($a1)
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lwc1 $f16,10225($k0)
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lwc2 $18,-841($a2)
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lwl $s4,-4231($t7)
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lwr $zero,-19147($gp)
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mfc1 $a3,$f27
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mfhi $s3
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mfhi $sp
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mflo $s1
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mov.d $f20,$f14
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mov.s $f2,$f27
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move $s8,$a0
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move $t9,$a2
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mtc1 $s8,$f9
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mthi $s1
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mtlo $sp
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mtlo $t9
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mul.d $f20,$f20,$f16
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mul.s $f30,$f10,$f2
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mult $sp,$s4
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mult $sp,$v0
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multu $gp,$k0
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multu $t1,$s2
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neg.d $f27,$f18
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neg.s $f1,$f15
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nop
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nor $a3,$zero,$a3
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or $t4,$s0,$sp
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sb $s6,-19857($t6)
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sh $t6,-6704($t7)
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sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
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sllv $a3,$t1 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
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sllv $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
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slt $s7,$t3,$k1
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slti $s1,$t2,9489
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sltiu $t9,$t9,-15531
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sltu $s4,$s5,$t3
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sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
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sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
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srav $s1,$sp # CHECK: srav $17, $17, $sp # encoding: [0x03,0xb1,0x88,0x07]
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srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
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srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
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srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
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srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
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srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
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ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
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sub $s6,$s3,$t4
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sub.d $f18,$f3,$f17
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sub.s $f23,$f22,$f22
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subu $sp,$s6,$s6
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sw $ra,-10160($sp)
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swc1 $f6,-8465($t8)
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swc2 $25,24880($s0)
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swl $t7,13694($s3)
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swr $s1,-26590($t6)
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xor $s2,$a0,$s8
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