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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
3.3 KiB
LLVM
80 lines
3.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc -mtriple=thumb-eabi -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=misched -arm-atomic-cfg-tidy=0 %s -o - 2>&1 | FileCheck %s
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;
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; Loop counter copies should be eliminated.
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; There is also a MUL here, but we don't care where it is scheduled.
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; CHECK: postinc
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; CHECK: *** Final schedule for BB#2 ***
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; CHECK: t2LDRs
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; CHECK: t2ADDrr
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; CHECK: t2CMPrr
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; CHECK: COPY
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define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind {
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entry:
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%cmp4 = icmp eq i32 %a, 0
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br i1 %cmp4, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ]
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%indvars.iv.next = add i32 %indvars.iv, %s
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%arrayidx = getelementptr inbounds i32, i32* %d, i32 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%mul = mul nsw i32 %0, %s.05
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%exitcond = icmp eq i32 %indvars.iv.next, %a
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
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ret i32 %s.0.lcssa
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}
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; This case was a crasher in constrainLocalCopy.
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; The problem was the t2LDR_PRE defining both the global and local lrg.
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; CHECK-LABEL: *** Final schedule for BB#5 ***
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; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
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; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
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; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
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; CHECK-LABEL: MACHINEINSTRS
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%struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
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%union.rtunion_def = type { i64 }
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; Function Attrs: nounwind ssp
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declare hidden fastcc void @df_ref_record(i32* nocapture, %struct.rtx_def*, %struct.rtx_def**, %struct.rtx_def*, i32, i32) #0
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; Function Attrs: nounwind ssp
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define hidden fastcc void @df_def_record_1(i32* nocapture %df, %struct.rtx_def* %x, %struct.rtx_def* %insn) #0 {
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entry:
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br label %while.cond
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while.cond: ; preds = %if.end28, %entry
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%loc.0 = phi %struct.rtx_def** [ %rtx31, %if.end28 ], [ undef, %entry ]
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%dst.0 = phi %struct.rtx_def* [ %0, %if.end28 ], [ undef, %entry ]
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switch i32 undef, label %if.end47 [
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i32 61, label %if.then46
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i32 64, label %if.then24
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i32 132, label %if.end28
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i32 133, label %if.end28
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]
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if.then24: ; preds = %while.cond
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br label %if.end28
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if.end28: ; preds = %if.then24, %while.cond, %while.cond
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%dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ]
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%arrayidx30 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
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%rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def**
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%0 = load %struct.rtx_def*, %struct.rtx_def** %rtx31, align 4
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br label %while.cond
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if.then46: ; preds = %while.cond
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tail call fastcc void @df_ref_record(i32* %df, %struct.rtx_def* %dst.0, %struct.rtx_def** %loc.0, %struct.rtx_def* %insn, i32 0, i32 undef)
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unreachable
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if.end47: ; preds = %while.cond
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ret void
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}
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attributes #0 = { nounwind ssp }
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