mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.0 KiB
LLVM
76 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9
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; rdar://8576755
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define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
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; A8-LABEL: test1:
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; A8: add r0, r0, r1, lsl r2
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; A9-LABEL: test1:
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; A9: add r0, r0, r1, lsl r2
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%shift.upgrd.1 = zext i8 %sh to i32
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%A = shl i32 %Y, %shift.upgrd.1
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%B = add i32 %X, %A
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ret i32 %B
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}
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define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
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; A8-LABEL: test2:
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; A8: bic r0, r0, r1, asr r2
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; A9-LABEL: test2:
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; A9: bic r0, r0, r1, asr r2
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%shift.upgrd.2 = zext i8 %sh to i32
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%A = ashr i32 %Y, %shift.upgrd.2
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%B = xor i32 %A, -1
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%C = and i32 %X, %B
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ret i32 %C
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}
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define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
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entry:
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; A8-LABEL: test3:
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; A8: ldr r0, [r0, r2, lsl #2]
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; A8: ldr r1, [r1, r2, lsl #2]
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; lsl #2 is free
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; A9-LABEL: test3:
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; A9: ldr r0, [r0, r2, lsl #2]
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; A9: ldr r1, [r1, r2, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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%tmp4 = add i32 %base2, %tmp1
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%tmp5 = inttoptr i32 %tmp4 to i32*
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%tmp6 = load i32, i32* %tmp3
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%tmp7 = load i32, i32* %tmp5
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%tmp8 = add i32 %tmp7, %tmp6
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ret i32 %tmp8
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}
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declare i8* @malloc(...)
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define fastcc void @test4(i16 %addr) nounwind {
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entry:
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; A8-LABEL: test4:
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; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
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; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
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; A8: str [[REG]], [r0, r1, lsl #2]
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; A8-NOT: str [[REG]], [r0]
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; A9-LABEL: test4:
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; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
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; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
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; A9: str [[REG]], [r0, r1, lsl #2]
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; A9-NOT: str [[REG]], [r0]
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%0 = tail call i8* (...)* @malloc(i32 undef) nounwind
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%1 = bitcast i8* %0 to i32*
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%2 = sext i16 %addr to i32
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%3 = getelementptr inbounds i32, i32* %1, i32 %2
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%4 = load i32, i32* %3, align 4
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%5 = add nsw i32 %4, 1
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store i32 %5, i32* %3, align 4
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ret void
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}
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