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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
4.0 KiB
LLVM
127 lines
4.0 KiB
LLVM
; RUN: llc -mcpu=core2 < %s | FileCheck %s
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; ModuleID = '<stdin>'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-macosx10.6.6"
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%0 = type { double }
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%union.anon = type { float }
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define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp {
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entry:
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%__x.addr.i = alloca double, align 8
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%__u.i = alloca %0, align 8
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%0 = bitcast double* %__x.addr.i to i8*
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%1 = bitcast %0* %__u.i to i8*
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store double %d1, double* %__x.addr.i, align 8
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%__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
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store double %d1, double* %__f.i, align 8
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%tmp = bitcast double %d1 to i64
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; CHECK-NOT: shr
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; CHECK: movmskpd
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; CHECK-NEXT: and
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%tmp1 = lshr i64 %tmp, 63
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%shr.i = trunc i64 %tmp1 to i32
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ret i32 %shr.i
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}
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define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp {
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entry:
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%__x.addr.i = alloca double, align 8
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%__u.i = alloca %0, align 8
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%add = fadd double %d1, %d2
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%0 = bitcast double* %__x.addr.i to i8*
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%1 = bitcast %0* %__u.i to i8*
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store double %add, double* %__x.addr.i, align 8
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%__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
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store double %add, double* %__f.i, align 8
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%tmp = bitcast double %add to i64
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; CHECK-NOT: shr
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; CHECK: movmskpd
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; CHECK-NEXT: and
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%tmp1 = lshr i64 %tmp, 63
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%shr.i = trunc i64 %tmp1 to i32
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ret i32 %shr.i
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}
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define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp {
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entry:
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%__x.addr.i = alloca float, align 4
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%__u.i = alloca %union.anon, align 4
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%0 = bitcast float* %__x.addr.i to i8*
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%1 = bitcast %union.anon* %__u.i to i8*
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store float %f1, float* %__x.addr.i, align 4
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%__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
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store float %f1, float* %__f.i, align 4
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%2 = bitcast float %f1 to i32
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; CHECK-NOT: shr
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; CHECK: movmskps
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; CHECK-NEXT: and
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%shr.i = lshr i32 %2, 31
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ret i32 %shr.i
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}
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define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp {
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entry:
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%__x.addr.i = alloca float, align 4
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%__u.i = alloca %union.anon, align 4
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%add = fadd float %f1, %f2
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%0 = bitcast float* %__x.addr.i to i8*
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%1 = bitcast %union.anon* %__u.i to i8*
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store float %add, float* %__x.addr.i, align 4
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%__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
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store float %add, float* %__f.i, align 4
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%2 = bitcast float %add to i32
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; CHECK-NOT: shr
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; CHECK: movmskps
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; CHECK-NEXT: and
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%shr.i = lshr i32 %2, 31
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ret i32 %shr.i
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}
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; PR11570
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define void @float_call_signbit(double %n) {
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entry:
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; FIXME: This should also use movmskps; we don't form the FGETSIGN node
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; in this case, though.
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; CHECK-LABEL: float_call_signbit:
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; CHECK: movd %xmm0, %rdi
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; FIXME
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%t0 = bitcast double %n to i64
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%tobool.i.i.i.i = icmp slt i64 %t0, 0
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tail call void @float_call_signbit_callee(i1 zeroext %tobool.i.i.i.i)
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ret void
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}
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declare void @float_call_signbit_callee(i1 zeroext)
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; rdar://10247336
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; movmskp{s|d} only set low 4/2 bits, high bits are known zero
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define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: movmskps
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; CHECK-NOT: movslq
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%0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
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%idxprom = sext i32 %0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %indexTable, i64 %idxprom
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%1 = load i32, i32* %arrayidx, align 4
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ret i32 %1
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}
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define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: movmskpd
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; CHECK-NOT: movslq
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%0 = bitcast <4 x float> %x to <2 x double>
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%1 = tail call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %0) nounwind
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%idxprom = sext i32 %1 to i64
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%arrayidx = getelementptr inbounds i32, i32* %indexTable, i64 %idxprom
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%2 = load i32, i32* %arrayidx, align 4
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ret i32 %2
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}
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declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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