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2e8bd89503
This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
312 lines
8.7 KiB
C++
312 lines
8.7 KiB
C++
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "PPCInstPrinter.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#include "PPCGenAsmWriter.inc"
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void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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// Check for slwi/srwi mnemonics.
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if (MI->getOpcode() == PPC::RLWINM) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char MB = MI->getOperand(3).getImm();
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unsigned char ME = MI->getOperand(4).getImm();
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bool useSubstituteMnemonic = false;
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if (SH <= 31 && MB == 0 && ME == (31-SH)) {
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O << "\tslwi "; useSubstituteMnemonic = true;
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}
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if (SH <= 31 && MB == (32-SH) && ME == 31) {
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O << "\tsrwi "; useSubstituteMnemonic = true;
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SH = 32-SH;
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}
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if (useSubstituteMnemonic) {
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
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O << "\tmr ";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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printAnnotation(O, Annot);
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return;
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}
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if (MI->getOpcode() == PPC::RLDICR) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char ME = MI->getOperand(3).getImm();
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// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
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if (63-SH == ME) {
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O << "\tsldi ";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O,
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const char *Modifier) {
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (StringRef(Modifier) == "cc") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LT:
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O << "lt";
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return;
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_LE:
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O << "le";
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return;
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_EQ:
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O << "eq";
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return;
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GE:
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O << "ge";
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return;
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_GT:
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O << "gt";
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return;
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_NE:
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O << "ne";
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return;
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_UN:
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O << "un";
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return;
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case PPC::PRED_NU_MINUS:
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case PPC::PRED_NU_PLUS:
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case PPC::PRED_NU:
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O << "nu";
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return;
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default:
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llvm_unreachable("Invalid predicate code");
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}
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}
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if (StringRef(Modifier) == "pm") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT:
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case PPC::PRED_LE:
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case PPC::PRED_EQ:
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case PPC::PRED_GE:
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case PPC::PRED_GT:
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case PPC::PRED_NE:
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case PPC::PRED_UN:
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case PPC::PRED_NU:
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return;
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_NU_MINUS:
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O << "-";
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return;
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_NU_PLUS:
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O << "+";
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return;
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default:
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llvm_unreachable("Invalid predicate code");
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}
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}
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assert(StringRef(Modifier) == "reg" &&
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"Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
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printOperand(MI, OpNo+1, O);
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}
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void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int Value = MI->getOperand(OpNo).getImm();
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Value = SignExtend32<5>(Value);
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O << (int)Value;
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}
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void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 31 && "Invalid u5imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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O << (short)MI->getOperand(OpNo).getImm();
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else
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printOperand(MI, OpNo, O);
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}
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void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << (unsigned short)MI->getOperand(OpNo).getImm();
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}
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void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (!MI->getOperand(OpNo).isImm())
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return printOperand(MI, OpNo, O);
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print .+8, an eight byte displacement from the PC.
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O << ".+";
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printAbsBranchOperand(MI, OpNo, O);
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}
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void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (!MI->getOperand(OpNo).isImm())
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return printOperand(MI, OpNo, O);
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O << (int)MI->getOperand(OpNo).getImm()*4;
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}
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void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned CCReg = MI->getOperand(OpNo).getReg();
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unsigned RegNo;
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switch (CCReg) {
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default: llvm_unreachable("Unknown CR register");
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case PPC::CR0: RegNo = 0; break;
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case PPC::CR1: RegNo = 1; break;
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case PPC::CR2: RegNo = 2; break;
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case PPC::CR3: RegNo = 3; break;
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case PPC::CR4: RegNo = 4; break;
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case PPC::CR5: RegNo = 5; break;
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case PPC::CR6: RegNo = 6; break;
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case PPC::CR7: RegNo = 7; break;
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}
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O << (0x80 >> RegNo);
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}
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void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printS16ImmOperand(MI, OpNo, O);
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O << '(';
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if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo+1, O);
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O << ')';
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}
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void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// When used as the base register, r0 reads constant zero rather than
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// the value contained in the register. For this reason, the darwin
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// assembler requires that we print r0 as 0 (no r) when used as the base.
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if (MI->getOperand(OpNo).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo, O);
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O << ", ";
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printOperand(MI, OpNo+1, O);
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}
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/// stripRegisterPrefix - This method strips the character prefix from a
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/// register name so that only the number is left. Used by for linux asm.
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static const char *stripRegisterPrefix(const char *RegName) {
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switch (RegName[0]) {
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case 'r':
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case 'f':
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case 'v': return RegName + 1;
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case 'c': if (RegName[1] == 'r') return RegName + 2;
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}
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return RegName;
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}
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void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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const char *RegName = getRegisterName(Op.getReg());
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// The linux and AIX assembler does not take register prefixes.
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if (!isDarwinSyntax())
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RegName = stripRegisterPrefix(RegName);
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O << RegName;
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return;
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}
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if (Op.isImm()) {
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O << Op.getImm();
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return;
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}
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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O << *Op.getExpr();
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}
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