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https://github.com/c64scene-ar/llvm-6502.git
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58f8a138a9
Summary: This patch first change the register that holds local address for stack frame to %SPL. Then the new NVPTXPeephole pass will try to scan the following pattern %vreg0<def> = LEA_ADDRi64 <fi#0>, 4 %vreg1<def> = cvta_to_local %vreg0 and transform it into %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4 Patched by Xuetian Weng Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: eliben, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10549 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240587 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
3.2 KiB
C++
89 lines
3.2 KiB
C++
//=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXFrameLowering.h"
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXSubtarget.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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NVPTXFrameLowering::NVPTXFrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0) {}
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bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
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void NVPTXFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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if (MF.getFrameInfo()->hasStackObjects()) {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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// Insert "mov.u32 %SP, %Depot"
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MachineInstr *MI = MBB.begin();
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MachineRegisterInfo &MR = MF.getRegInfo();
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// This instruction really occurs before first instruction
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// in the BB, so giving it no debug location.
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DebugLoc dl = DebugLoc();
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// mov %SPL, %depot;
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// cvta.local %SP, %SPL;
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if (static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit()) {
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// Check if %SP is actually used
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if (MR.hasOneNonDBGUse(NVPTX::VRFrame)) {
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MI = BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(
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NVPTX::cvta_local_yes_64),
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NVPTX::VRFrame)
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.addReg(NVPTX::VRFrameLocal);
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}
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BuildMI(MBB, MI, dl,
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MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64),
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NVPTX::VRFrameLocal)
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.addImm(MF.getFunctionNumber());
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} else {
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// Check if %SP is actually used
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if (MR.hasOneNonDBGUse(NVPTX::VRFrame)) {
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MI = BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(
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NVPTX::cvta_local_yes),
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NVPTX::VRFrame)
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.addReg(NVPTX::VRFrameLocal);
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}
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BuildMI(MBB, MI, dl,
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MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR),
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NVPTX::VRFrameLocal)
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.addImm(MF.getFunctionNumber());
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}
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}
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}
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void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {}
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// This function eliminates ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void NVPTXFrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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