Chris Lattner 7c423b4df1 Fix pifft by correcting the case when a i64/f64 straddles O5 and memory: ...

we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24859 91177308-0d34-0410-b5e6-96231b3b80d8

2005-12-19 07:57:53 +00:00

..

Alpha

fix FP selects

2005-12-12 20:30:09 +00:00

CBackend

…

IA64

Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.

2005-12-05 02:34:29 +00:00

PowerPC

This is handled by the autogen'd code

2005-12-18 21:06:11 +00:00

Skeleton

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

Sparc

Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:

2005-12-19 07:57:53 +00:00

SparcV8

Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:

2005-12-19 07:57:53 +00:00

SparcV9

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

X86

eliminate some redundancy

2005-12-17 19:47:05 +00:00

Makefile

…

MRegisterInfo.cpp

…

SubtargetFeature.cpp

…

Target.td

Added support to specify predicates.

2005-12-14 22:02:59 +00:00

TargetData.cpp

…

TargetFrameInfo.cpp

…

TargetInstrInfo.cpp

…

TargetMachine.cpp

…

TargetMachineRegistry.cpp

…

TargetSchedInfo.cpp

…

TargetSchedule.td

…

TargetSelectionDAG.td

add a node, for completeness

2005-12-18 07:05:21 +00:00

TargetSubtarget.cpp

…