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30a7a7c1fdbd2607345dd1554e3436749fd75c6e
llvm-6502/test/MC/Disassembler
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Mihai Popa 30a7a7c1fd VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:57:05 +00:00
..
AArch64
AArch64: implement ETMv4 trace system registers.
2013-04-03 12:31:29 +00:00
ARM
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
2013-05-20 14:57:05 +00:00
MBlaze
…
Mips
[mips] DSP-ASE move from HI/LO register instructions.
2013-04-18 00:52:44 +00:00
SystemZ
[SystemZ] Make use of SUBTRACT HALFWORD
2013-05-15 15:05:29 +00:00
X86
Add CLAC/STAC instruction encoding/decoding support
2013-04-11 04:52:28 +00:00
XCore
[XCore] Add LDAPB instructions.
2013-05-05 13:36:53 +00:00
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