Files
llvm-6502/test/CodeGen
Kalle Raiskila 31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU.
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 13:19:18 +00:00
..
2011-01-20 08:34:58 +00:00