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605c40341b
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223862 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.2 KiB
LLVM
75 lines
3.2 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN
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; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN
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; rdar://12713765
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; When realign-stack is set to false, make sure we are not creating stack
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; objects that are assumed to be 64-byte aligned.
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@T3_retval = common global <16 x float> zeroinitializer, align 16
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define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
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entry:
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; NO-REALIGN-LABEL: test1
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; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; REALIGN-LABEL: test2
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; REALIGN: bic sp, sp, #63
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; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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