mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
2b1874cbd4
Summary:
Atomic loads and store of up to the native size (32 bits, or 64 for PPC64)
can be lowered to a simple load or store instruction (as the synchronization
is already handled by AtomicExpand, and the atomicity is guaranteed thanks to
the alignment requirements of atomic accesses). This is exactly what this patch
does. Previously, these were implemented by complex
load-linked/store-conditional loops.. an obvious performance problem.
For example, this patch turns
```
define void @store_i8_unordered(i8* %mem) {
store atomic i8 42, i8* %mem unordered, align 1
ret void
}
```
from
```
_store_i8_unordered: ; @store_i8_unordered
; BB#0:
rlwinm r2, r3, 3, 27, 28
li r4, 42
xori r5, r2, 24
rlwinm r2, r3, 0, 0, 29
li r3, 255
slw r4, r4, r5
slw r3, r3, r5
and r4, r4, r3
LBB4_1: ; =>This Inner Loop Header: Depth=1
lwarx r5, 0, r2
andc r5, r5, r3
or r5, r4, r5
stwcx. r5, 0, r2
bne cr0, LBB4_1
; BB#2:
blr
```
into
```
_store_i8_unordered: ; @store_i8_unordered
; BB#0:
li r2, 42
stb r2, 0(r3)
blr
```
which looks like a pretty clear win to me.
Test Plan:
fixed the tests + new test for indexed accesses + make check-all
Reviewers: jfb, wschmidt, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218922 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.0 KiB
LLVM
49 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=ppc64 | FileCheck %s
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define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange_and_add:
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; CHECK: ldarx
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%tmp = atomicrmw add i64* %mem, i64 %val monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange_and_cmp(i64* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp:
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; CHECK: ldarx
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%tmppair = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
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%tmp = extractvalue { i64, i1 } %tmppair, 0
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange:
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; CHECK: ldarx
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%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define void @atomic_store(i64* %mem, i64 %val) nounwind {
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entry:
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; CHECK: @atomic_store
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store atomic i64 %val, i64* %mem release, align 64
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; CHECK: sync 1
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; CHECK-NOT: stdcx
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; CHECK: std
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ret void
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}
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define i64 @atomic_load(i64* %mem) nounwind {
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entry:
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; CHECK: @atomic_load
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%tmp = load atomic i64* %mem acquire, align 64
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; CHECK-NOT: ldarx
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; CHECK: ld
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; CHECK: sync 1
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ret i64 %tmp
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}
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