mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-22 13:29:44 +00:00
a0af4b0271
The sign-/zero-extension of the loaded value can be performed by the memory instruction for free. If the result of the load has only one use and the use is a sign-/zero-extend, then we emit the proper load instruction. The extend is only a register copy and will be optimized away later on. Other instructions that consume the sign-/zero-extended value are also made aware of this fact, so they don't fold the extend too. This fixes rdar://problem/18495928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218653 91177308-0d34-0410-b5e6-96231b3b80d8
191 lines
4.3 KiB
LLVM
191 lines
4.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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;
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; Test that we only use the sign/zero extend in the address calculation when
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; necessary.
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;
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; SHIFT
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;
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define i64 @load_addr_shift_zext1(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_zext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_shift_zext2(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_zext2
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3{{\]}}
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_shift_sext1(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_sext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = sext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_shift_sext2(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_sext2
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
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%1 = sext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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;
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; MUL
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;
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define i64 @load_addr_mul_zext1(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = zext i32 %a to i64
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%2 = mul i64 %1, 8
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_mul_zext2(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext2
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
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%1 = zext i32 %a to i64
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%2 = mul i64 %1, 8
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_mul_sext1(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_sext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = sext i32 %a to i64
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%2 = mul i64 %1, 8
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_mul_sext2(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_sext2
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
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%1 = sext i32 %a to i64
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%2 = mul i64 %1, 8
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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; Test folding of the sign-/zero-extend into the load instruction.
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define i32 @load_zext_i8_to_i32(i8* %a) {
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; CHECK-LABEL: load_zext_i8_to_i32
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; CHECK: ldrb w0, [x0]
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; CHECK-NOT: uxtb
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%1 = load i8* %a
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%2 = zext i8 %1 to i32
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ret i32 %2
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}
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define i32 @load_zext_i16_to_i32(i16* %a) {
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; CHECK-LABEL: load_zext_i16_to_i32
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; CHECK: ldrh w0, [x0]
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; CHECK-NOT: uxth
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%1 = load i16* %a
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%2 = zext i16 %1 to i32
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ret i32 %2
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}
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define i64 @load_zext_i8_to_i64(i8* %a) {
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; CHECK-LABEL: load_zext_i8_to_i64
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; CHECK: ldrb w0, [x0]
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; CHECK-NOT: uxtb
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%1 = load i8* %a
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%2 = zext i8 %1 to i64
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ret i64 %2
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}
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define i64 @load_zext_i16_to_i64(i16* %a) {
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; CHECK-LABEL: load_zext_i16_to_i64
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; CHECK: ldrh w0, [x0]
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; CHECK-NOT: uxth
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%1 = load i16* %a
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%2 = zext i16 %1 to i64
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ret i64 %2
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}
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define i64 @load_zext_i32_to_i64(i32* %a) {
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; CHECK-LABEL: load_zext_i32_to_i64
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; CHECK: ldr w0, [x0]
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; CHECK-NOT: uxtw
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%1 = load i32* %a
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%2 = zext i32 %1 to i64
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ret i64 %2
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}
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define i32 @load_sext_i8_to_i32(i8* %a) {
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; CHECK-LABEL: load_sext_i8_to_i32
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; CHECK: ldrsb w0, [x0]
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; CHECK-NOT: sxtb
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%1 = load i8* %a
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%2 = sext i8 %1 to i32
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ret i32 %2
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}
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define i32 @load_sext_i16_to_i32(i16* %a) {
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; CHECK-LABEL: load_sext_i16_to_i32
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; CHECK: ldrsh w0, [x0]
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; CHECK-NOT: sxth
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%1 = load i16* %a
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%2 = sext i16 %1 to i32
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ret i32 %2
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}
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define i64 @load_sext_i8_to_i64(i8* %a) {
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; CHECK-LABEL: load_sext_i8_to_i64
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; CHECK: ldrsb w0, [x0]
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; CHECK-NOT: sxtb
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%1 = load i8* %a
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%2 = sext i8 %1 to i64
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ret i64 %2
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}
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define i64 @load_sext_i16_to_i64(i16* %a) {
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; CHECK-LABEL: load_sext_i16_to_i64
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; CHECK: ldrsh w0, [x0]
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; CHECK-NOT: sxth
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%1 = load i16* %a
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%2 = sext i16 %1 to i64
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ret i64 %2
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}
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define i64 @load_sext_i32_to_i64(i32* %a) {
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; CHECK-LABEL: load_sext_i32_to_i64
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; CHECK: ldrsw x0, [x0]
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; CHECK-NOT: sxtw
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%1 = load i32* %a
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%2 = sext i32 %1 to i64
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ret i64 %2
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}
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