llvm-6502/lib/CodeGen
2007-03-26 22:37:45 +00:00
..
SelectionDAG SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 2007-03-26 07:12:51 +00:00
AsmPrinter.cpp
BranchFolding.cpp maintain LiveIn when splitting blocks (register scavenging needs it) 2007-03-20 21:35:06 +00:00
DwarfWriter.cpp
ELFWriter.cpp
ELFWriter.h
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp Fix for PR1257. Bug in live range shortening as a result of copy coalescing 2007-03-22 01:26:05 +00:00
LiveVariables.cpp
LLVMTargetMachine.cpp
MachineBasicBlock.cpp
MachineFunction.cpp
MachineInstr.cpp Change findRegisterUseOperand() to return operand index instead. 2007-03-26 22:37:45 +00:00
MachineModuleInfo.cpp
MachinePassRegistry.cpp
MachOWriter.cpp
MachOWriter.h
Makefile
Passes.cpp
PHIElimination.cpp
PhysRegTracker.h
PrologEpilogInserter.cpp
README.txt Potential spiller improvement. 2007-03-20 22:22:38 +00:00
RegAllocLinearScan.cpp First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00
RegAllocLocal.cpp
RegAllocSimple.cpp
RegisterScavenging.cpp Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 2007-03-26 22:23:54 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00
VirtRegMap.h First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00

Common register allocation / spilling problem:

	mul lr, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	ldr r4, [sp, #+52]
	mla r4, r3, lr, r4

can be:

	mul lr, r4, lr
        mov r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

and then "merge" mul and mov:

	mul r4, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.