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3382a84074
NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.0 KiB
LLVM
90 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=A8U
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8
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define float @t1(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2: t1:
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; VFP2: vnmla.f32
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; NEON: t1:
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; NEON: vnmla.f32
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; A8U: t1:
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; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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; A8: t1:
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; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fsub float -0.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define float @t2(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2: t2:
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; VFP2: vnmla.f32
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; NEON: t2:
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; NEON: vnmla.f32
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; A8U: t2:
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; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
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; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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; A8: t2:
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; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
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; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fmul float -1.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define double @t3(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2: t3:
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; VFP2: vnmla.f64
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; NEON: t3:
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; NEON: vnmla.f64
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; A8U: t3:
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; A8U: vnmul.f64 d
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; A8U: vsub.f64 d
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; A8: t3:
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; A8: vnmul.f64 d
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%1 = fsub double -0.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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define double @t4(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2: t4:
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; VFP2: vnmla.f64
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; NEON: t4:
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; NEON: vnmla.f64
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; A8U: t4:
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; A8U: vnmul.f64 d
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; A8U: vsub.f64 d
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; A8: t4:
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; A8: vnmul.f64 d
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%1 = fmul double -1.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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