Jakob Stoklund Olesen 33a537a5c4 Allow trailing physreg RegisterSDNode operands on non-variadic instructions. ...

Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.

The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.

Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8

2012-07-04 23:53:23 +00:00

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Analysis

PHINode::hasConstantValue(): return undef if the PHI is fully recursive.

2012-07-03 21:15:40 +00:00

Archive

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AsmParser

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Bitcode

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CodeGen

Allow trailing physreg RegisterSDNode operands on non-variadic instructions.

2012-07-04 23:53:23 +00:00

DebugInfo

Fix a bug in DebugInfo lib, extend a comment for one of the methods

2012-07-04 09:42:54 +00:00

ExecutionEngine

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Linker

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MC

MCContext.cpp: Fixup for my odd previous commit. No functional changes.

2012-07-03 06:01:27 +00:00

Object

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Support

Enable automatic GCC<->LLVM intrinsic translation for mips.

2012-06-28 19:09:53 +00:00

TableGen

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Target

Ensure CopyToReg nodes are always glued to the call instruction.

2012-07-04 19:28:31 +00:00

Transforms

Reverted r156659, due to probable performance regressions, DenseMap should be used here:

2012-07-04 05:53:05 +00:00

VMCore

PHINode::hasConstantValue(): return undef if the PHI is fully recursive.

2012-07-03 21:15:40 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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