Misha Brukman 33cc12319c The 'rd' register is consistently mentioned last in instruction definitions. ...

Created new classes from which instructions inherit their ordering of fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8

2003-05-31 06:25:19 +00:00

..

CBackend

Eliminate unnecessary ->get calls that are now automatically handled.

2003-05-29 15:12:27 +00:00

SparcV9

The 'rd' register is consistently mentioned last in instruction definitions.

2003-05-31 06:25:19 +00:00

X86

Renamed opIsDef to opIsDefOnly.

2003-05-27 00:03:17 +00:00

Makefile

X86 target builds fine now

2002-11-20 20:17:03 +00:00

MRegisterInfo.cpp

Capture more information in ctor

2002-12-28 20:34:18 +00:00

Target.td

Added the target-independent part of TableGen data.

2003-05-29 18:48:17 +00:00

TargetData.cpp

* Fix divide by zero error with empty structs

2003-05-21 18:08:44 +00:00

TargetInstrInfo.cpp

Rename MachineInstrInfo -> TargetInstrInfo

2003-01-14 22:00:31 +00:00

TargetMachine.cpp

The promotion rules are the same for all targets, they are set by the C standard.

2003-04-26 19:47:36 +00:00

TargetSchedInfo.cpp

More renamings of Target/Machine*Info to Target/Target*Info

2002-12-29 03:13:05 +00:00