llvm-6502/test/CodeGen/R600/literals.ll
Tom Stellard 6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:27 +00:00

34 lines
832 B
LLVM

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; Test using an integer literal constant.
; Generated ASM should be:
; ADD_INT KC0[2].Z literal.x, 5
; or
; ADD_INT literal.x KC0[2].Z, 5
; CHECK: @i32_literal
; CHECK: ADD_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
; CHECK-NEXT: 5
define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
entry:
%0 = add i32 5, %in
store i32 %0, i32 addrspace(1)* %out
ret void
}
; Test using a float literal constant.
; Generated ASM should be:
; ADD KC0[2].Z literal.x, 5.0
; or
; ADD literal.x KC0[2].Z, 5.0
; CHECK: @float_literal
; CHECK: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
; CHECK-NEXT: 1084227584(5.0
define void @float_literal(float addrspace(1)* %out, float %in) {
entry:
%0 = fadd float 5.0, %in
store float %0, float addrspace(1)* %out
ret void
}