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			269 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
			
		
		
	
	
			269 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
| //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
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| //
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file is distributed under the University of Illinois Open Source
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| // License. See LICENSE.TXT for details.
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| // This file defines wrappers for the Target class and related global
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| // functionality.  This makes it easier to access the data and provides a single
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| // place that needs to check it for validity.  All of these classes throw
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| // exceptions on error conditions.
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| #ifndef CODEGEN_TARGET_H
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| #define CODEGEN_TARGET_H
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| 
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| #include "CodeGenRegisters.h"
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| #include "CodeGenInstruction.h"
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| #include "Record.h"
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| #include "llvm/Support/raw_ostream.h"
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| #include <algorithm>
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| 
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| namespace llvm {
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| 
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| struct CodeGenRegister;
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| class CodeGenTarget;
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| 
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| // SelectionDAG node properties.
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| //  SDNPMemOperand: indicates that a node touches memory and therefore must
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| //                  have an associated memory operand that describes the access.
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| enum SDNP {
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|   SDNPCommutative, 
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|   SDNPAssociative, 
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|   SDNPHasChain,
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|   SDNPOutFlag,
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|   SDNPInFlag,
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|   SDNPOptInFlag,
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|   SDNPMayLoad,
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|   SDNPMayStore,
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|   SDNPSideEffect,
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|   SDNPMemOperand,
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|   SDNPVariadic,
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|   SDNPWantRoot,
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|   SDNPWantParent
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| };
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| 
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| /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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| /// record corresponds to.
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| MVT::SimpleValueType getValueType(Record *Rec);
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| 
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| std::string getName(MVT::SimpleValueType T);
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| std::string getEnumName(MVT::SimpleValueType T);
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| 
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| /// getQualifiedName - Return the name of the specified record, with a
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| /// namespace qualifier if the record contains one.
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| std::string getQualifiedName(const Record *R);
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|   
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| /// CodeGenTarget - This class corresponds to the Target class in the .td files.
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| ///
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| class CodeGenTarget {
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|   Record *TargetRec;
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| 
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|   mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
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|   mutable std::vector<CodeGenRegister> Registers;
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|   mutable std::vector<Record*> SubRegIndices;
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|   mutable std::vector<CodeGenRegisterClass> RegisterClasses;
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|   mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
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|   void ReadRegisters() const;
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|   void ReadSubRegIndices() const;
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|   void ReadRegisterClasses() const;
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|   void ReadInstructions() const;
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|   void ReadLegalValueTypes() const;
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|   
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|   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
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| public:
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|   CodeGenTarget();
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| 
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|   Record *getTargetRecord() const { return TargetRec; }
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|   const std::string &getName() const;
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| 
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|   /// getInstNamespace - Return the target-specific instruction namespace.
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|   ///
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|   std::string getInstNamespace() const;
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| 
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|   /// getInstructionSet - Return the InstructionSet object.
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|   ///
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|   Record *getInstructionSet() const;
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| 
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|   /// getAsmParser - Return the AssemblyParser definition for this target.
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|   ///
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|   Record *getAsmParser() const;
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| 
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|   /// getAsmWriter - Return the AssemblyWriter definition for this target.
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|   ///
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|   Record *getAsmWriter() const;
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| 
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|   const std::vector<CodeGenRegister> &getRegisters() const {
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|     if (Registers.empty()) ReadRegisters();
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|     return Registers;
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|   }
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|   
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|   /// getRegisterByName - If there is a register with the specific AsmName,
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|   /// return it.
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|   const CodeGenRegister *getRegisterByName(StringRef Name) const;
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| 
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|   const std::vector<Record*> &getSubRegIndices() const {
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|     if (SubRegIndices.empty()) ReadSubRegIndices();
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|     return SubRegIndices;
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|   }
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| 
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|   // Map a SubRegIndex Record to its number.
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|   unsigned getSubRegIndexNo(Record *idx) const {
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|     if (SubRegIndices.empty()) ReadSubRegIndices();
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|     std::vector<Record*>::const_iterator i =
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|       std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
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|     assert(i != SubRegIndices.end() && "Not a SubRegIndex");
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|     return (i - SubRegIndices.begin()) + 1;
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|   }
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| 
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|   const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
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|     if (RegisterClasses.empty()) ReadRegisterClasses();
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|     return RegisterClasses;
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|   }
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| 
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|   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
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|     const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
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|     for (unsigned i = 0, e = RC.size(); i != e; ++i)
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|       if (RC[i].TheDef == R)
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|         return RC[i];
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|     assert(0 && "Didn't find the register class");
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|     abort();
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|   }
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|   
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|   /// getRegisterClassForRegister - Find the register class that contains the
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|   /// specified physical register.  If the register is not in a register
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|   /// class, return null. If the register is in multiple classes, and the
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|   /// classes have a superset-subset relationship and the same set of
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|   /// types, return the superclass.  Otherwise return null.
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|   const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
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|     const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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|     const CodeGenRegisterClass *FoundRC = 0;
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|     for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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|       const CodeGenRegisterClass &RC = RegisterClasses[i];
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|       for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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|         if (R != RC.Elements[ei])
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|           continue;
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| 
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|         // If a register's classes have different types, return null.
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|         if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
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|           return 0;
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| 
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|         // If this is the first class that contains the register,
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|         // make a note of it and go on to the next class.
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|         if (!FoundRC) {
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|           FoundRC = &RC;
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|           break;
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|         }
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| 
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|         std::vector<Record *> Elements(RC.Elements);
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|         std::vector<Record *> FoundElements(FoundRC->Elements);
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|         std::sort(Elements.begin(), Elements.end());
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|         std::sort(FoundElements.begin(), FoundElements.end());
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| 
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|         // Check to see if the previously found class that contains
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|         // the register is a subclass of the current class. If so,
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|         // prefer the superclass.
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|         if (std::includes(Elements.begin(), Elements.end(),
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|                           FoundElements.begin(), FoundElements.end())) {
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|           FoundRC = &RC;
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|           break;
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|         }
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| 
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|         // Check to see if the previously found class that contains
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|         // the register is a superclass of the current class. If so,
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|         // prefer the superclass.
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|         if (std::includes(FoundElements.begin(), FoundElements.end(),
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|                           Elements.begin(), Elements.end()))
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|           break;
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| 
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|         // Multiple classes, and neither is a superclass of the other.
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|         // Return null.
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|         return 0;
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|       }
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|     }
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|     return FoundRC;
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|   }
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| 
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|   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
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|   /// specified physical register.
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|   std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
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|   
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|   const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
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|     if (LegalValueTypes.empty()) ReadLegalValueTypes();
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|     return LegalValueTypes;
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|   }
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|   
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|   /// isLegalValueType - Return true if the specified value type is natively
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|   /// supported by the target (i.e. there are registers that directly hold it).
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|   bool isLegalValueType(MVT::SimpleValueType VT) const {
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|     const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
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|     for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
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|       if (LegalVTs[i] == VT) return true;
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|     return false;    
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|   }
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| 
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| private:
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|   DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
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|     if (Instructions.empty()) ReadInstructions();
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|     return Instructions;
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|   }
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| public:
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|   
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|   CodeGenInstruction &getInstruction(const Record *InstRec) const {
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|     if (Instructions.empty()) ReadInstructions();
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|     DenseMap<const Record*, CodeGenInstruction*>::iterator I =
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|       Instructions.find(InstRec);
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|     assert(I != Instructions.end() && "Not an instruction");
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|     return *I->second;
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|   }
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| 
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|   /// getInstructionsByEnumValue - Return all of the instructions defined by the
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|   /// target, ordered by their enum value.
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|   const std::vector<const CodeGenInstruction*> &
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|   getInstructionsByEnumValue() const {
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|     if (InstrsByEnum.empty()) ComputeInstrsByEnum();
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|     return InstrsByEnum;
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|   }
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| 
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|   typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
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|   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
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|   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
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|   
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|   
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|   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
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|   ///
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|   bool isLittleEndianEncoding() const;
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|   
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| private:
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|   void ComputeInstrsByEnum() const;
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| };
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| 
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| /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
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| /// tablegen class in TargetSelectionDAG.td
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| class ComplexPattern {
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|   MVT::SimpleValueType Ty;
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|   unsigned NumOperands;
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|   std::string SelectFunc;
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|   std::vector<Record*> RootNodes;
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|   unsigned Properties; // Node properties
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| public:
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|   ComplexPattern() : NumOperands(0) {}
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|   ComplexPattern(Record *R);
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| 
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|   MVT::SimpleValueType getValueType() const { return Ty; }
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|   unsigned getNumOperands() const { return NumOperands; }
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|   const std::string &getSelectFunc() const { return SelectFunc; }
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|   const std::vector<Record*> &getRootNodes() const {
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|     return RootNodes;
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|   }
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|   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
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| };
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| 
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| } // End llvm namespace
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| 
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| #endif
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