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llvm-6502/include/llvm/CodeGen
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Rafael Espindola cce5873de3 Move getSymbolWithGlobalValueBase to TargetLoweringObjectFile. 
This allows it to be used in TargetLoweringObjectFileImpl.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 16:25:47 +00:00
..
PBQP
Dereference the node iterator when dumping the PBQP graph structure in DOT
2013-11-21 06:30:14 +00:00
Analysis.h
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AsmPrinter.h
Move getSymbolWithGlobalValueBase to TargetLoweringObjectFile.
2013-12-02 16:25:47 +00:00
CalcSpillWeights.h
CalcSpillWeights: allow overidding the spill weight normalizing function
2013-11-11 19:56:14 +00:00
CallingConvLower.h
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CommandFlags.h
Speling fixes.
2013-10-22 15:18:03 +00:00
DAGCombine.h
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DFAPacketizer.h
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EdgeBundles.h
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FastISel.h
Avoid illegal integer promotion in fastisel
2013-11-15 19:09:27 +00:00
FunctionLoweringInfo.h
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GCMetadata.h
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GCMetadataPrinter.h
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GCs.h
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GCStrategy.h
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IntrinsicLowering.h
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ISDOpcodes.h
Add addrspacecast instruction.
2013-11-15 01:34:59 +00:00
JITCodeEmitter.h
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LatencyPriorityQueue.h
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LexicalScopes.h
Remove capability for polymorphic destruction from LexicalScope
2013-11-20 00:54:28 +00:00
LinkAllAsmWriterComponents.h
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LinkAllCodegenComponents.h
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LiveInterval.h
Replacing HUGE_VALF with llvm::huge_valf in order to work around a warning triggered in MSVC 12.
2013-11-13 00:15:44 +00:00
LiveIntervalAnalysis.h
Represent RegUnit liveness with LiveRange instance
2013-10-10 21:29:02 +00:00
LiveIntervalUnion.h
Rename LiveRange to LiveInterval::Segment
2013-10-10 21:28:43 +00:00
LiveRangeEdit.h
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LiveRegMatrix.h
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LiveRegUnits.h
LiveRegUnits: Use *MBB for consistency and convenience.
2013-10-14 22:18:59 +00:00
LiveStackAnalysis.h
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LiveVariables.h
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MachineBasicBlock.h
Even more spelling fixes for "instruction".
2013-09-28 13:42:22 +00:00
MachineBlockFrequencyInfo.h
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MachineBranchProbabilityInfo.h
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MachineCodeEmitter.h
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MachineCodeInfo.h
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MachineConstantPool.h
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MachineDominators.h
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MachineFrameInfo.h
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MachineFunction.h
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MachineFunctionAnalysis.h
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MachineFunctionPass.h
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MachineInstr.h
Rename parameter: defined regs are not incoming.
2013-10-10 21:28:38 +00:00
MachineInstrBuilder.h
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MachineInstrBundle.h
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MachineJumpTableInfo.h
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MachineLoopInfo.h
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MachineMemOperand.h
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MachineModuleInfo.h
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MachineModuleInfoImpls.h
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MachineOperand.h
Fix a typo where we were creating <def,kill> operands instead of
2013-11-22 00:46:32 +00:00
MachinePassRegistry.h
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MachinePostDominators.h
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MachineRegisterInfo.h
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
MachineRelocation.h
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MachineScheduler.h
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
MachineSSAUpdater.h
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MachineTraceMetrics.h
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MachORelocation.h
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Passes.h
Move the old pass manager infrastructure into a legacy namespace and
2013-11-09 12:26:54 +00:00
PseudoSourceValue.h
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RegAllocPBQP.h
Re-apply r194300 with fixes for warnings.
2013-11-09 03:08:56 +00:00
RegAllocRegistry.h
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RegisterClassInfo.h
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RegisterPressure.h
Represent RegUnit liveness with LiveRange instance
2013-10-10 21:29:02 +00:00
RegisterScavenging.h
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ResourcePriorityQueue.h
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RuntimeLibcalls.h
Fix filename in header comment
2013-11-16 15:40:54 +00:00
ScheduleDAG.h
Explicitly request unsigned enum types when desired
2013-10-08 20:15:11 +00:00
ScheduleDAGInstrs.h
Even more spelling fixes for "instruction".
2013-09-28 13:42:22 +00:00
ScheduleDFS.h
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ScheduleHazardRecognizer.h
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SchedulerRegistry.h
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ScoreboardHazardRecognizer.h
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SelectionDAG.h
Split SETCC if VSELECT requires splitting too.
2013-11-22 00:39:23 +00:00
SelectionDAGISel.h
Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
2013-10-05 05:38:16 +00:00
SelectionDAGNodes.h
Add addrspacecast instruction.
2013-11-15 01:34:59 +00:00
SlotIndexes.h
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StackMaps.h
Refactor a lot of patchpoint/stackmap related code to simplify and make it
2013-11-29 03:07:54 +00:00
StackProtector.h
Reformat code with clang-format.
2013-10-30 02:25:14 +00:00
TargetLoweringObjectFileImpl.h
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TargetSchedule.h
IfConverter: Use TargetSchedule for instruction latencies
2013-09-30 15:28:56 +00:00
ValueTypes.h
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
2013-10-10 17:00:52 +00:00
ValueTypes.td
Implement aarch64 neon instruction set AdvSIMD (Across).
2013-10-05 08:22:10 +00:00
VirtRegMap.h
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