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cac51be31f
The patch disabled unrolling in loop vectorization pass when VF==1 on x86 architecture, by setting MaxInterleaveFactor to 1. Unrolling in loop vectorization pass may introduce the cost of overflow check, memory boundary check and extra prologue/epilogue code when regular unroller will unroll the loop another time. Disable it when VF==1 remove the unnecessary cost on x86. The same can be done for other platforms after verifying interleaving/memory bound checking to be not perf critical on those platforms. Differential Revision: http://reviews.llvm.org/D9515 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236613 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
2.9 KiB
C++
83 lines
2.9 KiB
C++
//===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// \file
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// This file implements a TargetTransformInfo analysis pass specific to the
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// AMDGPU target machine. It uses the target's detailed information to provide
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// more precise answers to certain TTI queries, while letting the target
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// independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetTransformInfo.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "AMDGPUtti"
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void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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UP.Threshold = 300; // Twice the default.
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UP.MaxCount = UINT_MAX;
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UP.Partial = true;
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// TODO: Do we want runtime unrolling?
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for (const BasicBlock *BB : L->getBlocks()) {
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const DataLayout &DL = BB->getModule()->getDataLayout();
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for (const Instruction &I : *BB) {
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const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
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if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
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continue;
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const Value *Ptr = GEP->getPointerOperand();
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const AllocaInst *Alloca =
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dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr, DL));
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if (Alloca) {
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// We want to do whatever we can to limit the number of alloca
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// instructions that make it through to the code generator. allocas
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// require us to use indirect addressing, which is slow and prone to
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// compiler bugs. If this loop does an address calculation on an
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// alloca ptr, then we want to use a higher than normal loop unroll
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// threshold. This will give SROA a better chance to eliminate these
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// allocas.
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//
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// Don't use the maximum allowed value here as it will make some
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// programs way too big.
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UP.Threshold = 800;
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}
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}
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}
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}
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unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
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if (Vec)
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return 0;
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// Number of VGPRs on SI.
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if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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return 256;
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return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
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}
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unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }
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unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
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// Semi-arbitrary large amount.
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return 64;
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}
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