Colin LeMahieu 35e1281ec7 [Hexagon] Adding vector predicate instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227613 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-30 21:24:06 +00:00
..
AArch64
ARM	ARM: further correct .fpu directive handling	2015-01-30 19:35:18 +00:00
AsmParser
COFF
Disassembler	[Hexagon] Adding vector predicate instructions.	2015-01-30 21:24:06 +00:00
ELF	Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with"	2015-01-26 09:30:29 +00:00
Hexagon
MachO	Add r224985 back with fixes.	2015-01-19 21:11:14 +00:00
Markup
Mips	[mips] Manually replace JAL pseudo-instructions with their JALR equivalent, instead of using InstAlias.	2015-01-30 11:18:50 +00:00
PowerPC
R600
Sparc
SystemZ
X86	[x86] Change u8imm operands to always print as unsigned. This makes shuffle masks and the like make way more sense.	2015-01-23 08:00:59 +00:00