Hal Finkel 360ee97179 [PowerPC] Generate logical vector VSX instructions ... These instructions are essentially the same as their Altivec counterparts, but have access to the larger VSX register file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204782 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-26 04:55:40 +00:00
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AArch64	Register Allocator: check other options before using a CSR for the first time.	2014-03-25 00:16:25 +00:00
ARM	test: fix CHECK lines	2014-03-25 03:39:39 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Correct lowering of VECTOR_SHUFFLE to VSHF.	2014-03-21 16:56:51 +00:00
MSP430
NVPTX	Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.	2014-03-24 16:52:30 +00:00
PowerPC	[PowerPC] Generate logical vector VSX instructions	2014-03-26 04:55:40 +00:00
R600	R600: Add failing testcase for <3 x i32> stores.	2014-03-25 16:50:55 +00:00
SPARC
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
Thumb
Thumb2
X86	Prevent alias from pointing to weak aliases.	2014-03-26 04:48:47 +00:00
XCore