Hal Finkel 360ee97179 [PowerPC] Generate logical vector VSX instructions ...

These instructions are essentially the same as their Altivec counterparts, but
have access to the larger VSX register file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204782 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-26 04:55:40 +00:00

..

AArch64

Register Allocator: check other options before using a CSR for the first time.

2014-03-25 00:16:25 +00:00

ARM

test: fix CHECK lines

2014-03-25 03:39:39 +00:00

CPP

…

Generic

CommandLine: Exit successfully for -version and -help

2014-02-28 19:08:01 +00:00

Hexagon

Fix broken CHECK lines

2014-02-16 07:31:05 +00:00

Inputs

…

Mips

[mips] Correct lowering of VECTOR_SHUFFLE to VSHF.

2014-03-21 16:56:51 +00:00

MSP430

Fix known typos

2014-01-24 17:20:08 +00:00

NVPTX

Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.

2014-03-24 16:52:30 +00:00

PowerPC

[PowerPC] Generate logical vector VSX instructions

2014-03-26 04:55:40 +00:00

R600

R600: Add failing testcase for <3 x i32> stores.

2014-03-25 16:50:55 +00:00

SPARC

Remove the linker_private and linker_private_weak linkages.

2014-03-13 23:18:37 +00:00

SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

Thumb

Add triples to try to fix the windows bots.

2014-02-13 16:49:47 +00:00

Thumb2

ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block

2014-02-26 11:27:28 +00:00

X86

Prevent alias from pointing to weak aliases.

2014-03-26 04:48:47 +00:00

XCore

[XCore] Add support for the "m" inline asm constraint.

2014-03-06 16:37:48 +00:00