mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
a2846b4bee
This is before LiveVariables anyway, where these kill flags are recalculated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
529 lines
13 KiB
C++
529 lines
13 KiB
C++
//===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "neon-prealloc"
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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namespace {
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class NEONPreAllocPass : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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public:
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static char ID;
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NEONPreAllocPass() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "NEON register pre-allocation pass";
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}
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private:
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bool FormsRegSequence(MachineInstr *MI,
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unsigned FirstOpnd, unsigned NumRegs,
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unsigned Offset, unsigned Stride) const;
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bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
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};
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char NEONPreAllocPass::ID = 0;
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}
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static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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unsigned &Offset, unsigned &Stride) {
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// Default to unit stride with no offset.
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Stride = 1;
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Offset = 0;
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switch (Opcode) {
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default:
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break;
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case ARM::VLD1q8:
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case ARM::VLD1q16:
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case ARM::VLD1q32:
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case ARM::VLD1q64:
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case ARM::VLD2d8:
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case ARM::VLD2d16:
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case ARM::VLD2d32:
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case ARM::VLD2LNd8:
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case ARM::VLD2LNd16:
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case ARM::VLD2LNd32:
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FirstOpnd = 0;
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NumRegs = 2;
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return true;
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case ARM::VLD2q8:
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case ARM::VLD2q16:
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case ARM::VLD2q32:
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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case ARM::VLD2LNq16:
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case ARM::VLD2LNq32:
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FirstOpnd = 0;
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NumRegs = 2;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD2LNq16odd:
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case ARM::VLD2LNq32odd:
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FirstOpnd = 0;
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NumRegs = 2;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD3d8:
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case ARM::VLD3d16:
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case ARM::VLD3d32:
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case ARM::VLD1d64T:
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case ARM::VLD3LNd8:
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case ARM::VLD3LNd16:
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case ARM::VLD3LNd32:
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FirstOpnd = 0;
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NumRegs = 3;
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return true;
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case ARM::VLD3q8_UPD:
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case ARM::VLD3q16_UPD:
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case ARM::VLD3q32_UPD:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3q8odd_UPD:
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case ARM::VLD3q16odd_UPD:
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case ARM::VLD3q32odd_UPD:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD3LNq16:
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case ARM::VLD3LNq32:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3LNq16odd:
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case ARM::VLD3LNq32odd:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD4d8:
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case ARM::VLD4d16:
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case ARM::VLD4d32:
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case ARM::VLD1d64Q:
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case ARM::VLD4LNd8:
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case ARM::VLD4LNd16:
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case ARM::VLD4LNd32:
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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case ARM::VLD4q8_UPD:
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case ARM::VLD4q16_UPD:
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case ARM::VLD4q32_UPD:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD4q8odd_UPD:
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case ARM::VLD4q16odd_UPD:
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case ARM::VLD4q32odd_UPD:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD4LNq16:
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case ARM::VLD4LNq32:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD4LNq16odd:
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case ARM::VLD4LNq32odd:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST1q8:
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case ARM::VST1q16:
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case ARM::VST1q32:
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case ARM::VST1q64:
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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FirstOpnd = 2;
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NumRegs = 2;
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return true;
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case ARM::VST2q8:
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case ARM::VST2q16:
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case ARM::VST2q32:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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case ARM::VST2LNq16:
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case ARM::VST2LNq32:
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FirstOpnd = 2;
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NumRegs = 2;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST2LNq16odd:
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case ARM::VST2LNq32odd:
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FirstOpnd = 2;
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NumRegs = 2;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST3d8:
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case ARM::VST3d16:
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case ARM::VST3d32:
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case ARM::VST1d64T:
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case ARM::VST3LNd8:
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case ARM::VST3LNd16:
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case ARM::VST3LNd32:
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FirstOpnd = 2;
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NumRegs = 3;
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return true;
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case ARM::VST3q8_UPD:
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case ARM::VST3q16_UPD:
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case ARM::VST3q32_UPD:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST3q8odd_UPD:
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case ARM::VST3q16odd_UPD:
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case ARM::VST3q32odd_UPD:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST3LNq16:
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case ARM::VST3LNq32:
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FirstOpnd = 2;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST3LNq16odd:
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case ARM::VST3LNq32odd:
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FirstOpnd = 2;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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case ARM::VST1d64Q:
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case ARM::VST4LNd8:
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case ARM::VST4LNd16:
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case ARM::VST4LNd32:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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case ARM::VST4q8_UPD:
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case ARM::VST4q16_UPD:
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case ARM::VST4q32_UPD:
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FirstOpnd = 4;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST4q8odd_UPD:
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case ARM::VST4q16odd_UPD:
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case ARM::VST4q32odd_UPD:
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FirstOpnd = 4;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST4LNq16:
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case ARM::VST4LNq32:
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FirstOpnd = 2;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST4LNq16odd:
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case ARM::VST4LNq32odd:
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FirstOpnd = 2;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VTBL2:
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FirstOpnd = 1;
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NumRegs = 2;
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return true;
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case ARM::VTBL3:
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FirstOpnd = 1;
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NumRegs = 3;
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return true;
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case ARM::VTBL4:
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FirstOpnd = 1;
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NumRegs = 4;
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return true;
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case ARM::VTBX2:
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FirstOpnd = 2;
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NumRegs = 2;
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return true;
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case ARM::VTBX3:
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FirstOpnd = 2;
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NumRegs = 3;
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return true;
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case ARM::VTBX4:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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}
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return false;
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}
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bool
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NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
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unsigned FirstOpnd, unsigned NumRegs,
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unsigned Offset, unsigned Stride) const {
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MachineOperand &FMO = MI->getOperand(FirstOpnd);
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assert(FMO.isReg() && FMO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = FMO.getReg();
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(void)VirtReg;
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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unsigned LastSubIdx = 0;
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if (FMO.isDef()) {
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MachineInstr *RegSeq = 0;
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for (unsigned R = 0; R < NumRegs; ++R) {
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const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// Feeding into a REG_SEQUENCE.
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if (!MRI->hasOneNonDBGUse(VirtReg))
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return false;
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MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
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if (!UseMI->isRegSequence())
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return false;
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if (RegSeq && RegSeq != UseMI)
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return false;
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unsigned OpIdx = 1 + (Offset + R * Stride) * 2;
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if (UseMI->getOperand(OpIdx).getReg() != VirtReg)
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llvm_unreachable("Malformed REG_SEQUENCE instruction!");
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unsigned SubIdx = UseMI->getOperand(OpIdx + 1).getImm();
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if (LastSubIdx) {
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if (LastSubIdx != SubIdx-Stride)
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return false;
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} else {
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// Must start from dsub_0 or qsub_0.
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if (SubIdx != (ARM::dsub_0+Offset) &&
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SubIdx != (ARM::qsub_0+Offset))
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return false;
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}
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RegSeq = UseMI;
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LastSubIdx = SubIdx;
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}
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// In the case of vld3, etc., make sure the trailing operand of
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// REG_SEQUENCE is an undef.
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if (NumRegs == 3) {
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unsigned OpIdx = 1 + (Offset + 3 * Stride) * 2;
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const MachineOperand &MO = RegSeq->getOperand(OpIdx);
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unsigned VirtReg = MO.getReg();
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MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
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if (!DefMI || !DefMI->isImplicitDef())
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return false;
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}
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return true;
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}
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unsigned LastSrcReg = 0;
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SmallVector<unsigned, 4> SubIds;
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for (unsigned R = 0; R < NumRegs; ++R) {
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const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// Extracting from a Q or QQ register.
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MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
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if (!DefMI || !DefMI->isExtractSubreg())
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return false;
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VirtReg = DefMI->getOperand(1).getReg();
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if (LastSrcReg && LastSrcReg != VirtReg)
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return false;
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LastSrcReg = VirtReg;
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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if (RC != ARM::QPRRegisterClass &&
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RC != ARM::QQPRRegisterClass &&
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RC != ARM::QQQQPRRegisterClass)
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return false;
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unsigned SubIdx = DefMI->getOperand(2).getImm();
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if (LastSubIdx) {
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if (LastSubIdx != SubIdx-Stride)
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return false;
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} else {
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// Must start from dsub_0 or qsub_0.
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if (SubIdx != (ARM::dsub_0+Offset) &&
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SubIdx != (ARM::qsub_0+Offset))
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return false;
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}
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SubIds.push_back(SubIdx);
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LastSubIdx = SubIdx;
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}
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// FIXME: Update the uses of EXTRACT_SUBREG from REG_SEQUENCE is
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// currently required for correctness. e.g.
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// %reg1041<def> = REG_SEQUENCE %reg1040<kill>, 5, %reg1035<kill>, 6
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// %reg1042<def> = EXTRACT_SUBREG %reg1041, 6
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// %reg1043<def> = EXTRACT_SUBREG %reg1041, 5
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// VST1q16 %reg1025<kill>, 0, %reg1043<kill>, %reg1042<kill>,
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// reg1042 and reg1043 should be replaced with reg1041:6 and reg1041:5
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// respectively.
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// We need to change how we model uses of REG_SEQUENCE.
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for (unsigned R = 0; R < NumRegs; ++R) {
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MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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unsigned OldReg = MO.getReg();
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MachineInstr *DefMI = MRI->getVRegDef(OldReg);
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assert(DefMI->isExtractSubreg());
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MO.setReg(LastSrcReg);
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MO.setSubReg(SubIds[R]);
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MO.setIsKill(false);
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// Delete the EXTRACT_SUBREG if its result is now dead.
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if (MRI->use_empty(OldReg))
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DefMI->eraseFromParent();
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}
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return true;
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}
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bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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for (; MBBI != E; ++MBBI) {
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MachineInstr *MI = &*MBBI;
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unsigned FirstOpnd, NumRegs, Offset, Stride;
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if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
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continue;
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if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
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continue;
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MachineBasicBlock::iterator NextI = llvm::next(MBBI);
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for (unsigned R = 0; R < NumRegs; ++R) {
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MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// For now, just assign a fixed set of adjacent registers.
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// This leaves plenty of room for future improvements.
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static const unsigned NEONDRegs[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7
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};
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MO.setReg(NEONDRegs[Offset + R * Stride]);
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if (MO.isUse()) {
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// Insert a copy from VirtReg.
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TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
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ARM::DPRRegisterClass, ARM::DPRRegisterClass,
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DebugLoc());
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if (MO.isKill()) {
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MachineInstr *CopyMI = prior(MBBI);
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CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
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}
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MO.setIsKill();
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} else if (MO.isDef() && !MO.isDead()) {
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// Add a copy to VirtReg.
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TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
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ARM::DPRRegisterClass, ARM::DPRRegisterClass,
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DebugLoc());
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}
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}
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}
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return Modified;
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}
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bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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MRI = &MF.getRegInfo();
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bool Modified = false;
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for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
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++MFI) {
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MachineBasicBlock &MBB = *MFI;
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Modified |= PreAllocNEONRegisters(MBB);
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}
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return Modified;
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}
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/// createNEONPreAllocPass - returns an instance of the NEON register
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/// pre-allocation pass.
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FunctionPass *llvm::createNEONPreAllocPass() {
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return new NEONPreAllocPass();
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}
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