Devang Patel a28101e61a Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8

2012-01-27 19:48:28 +00:00

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3DNow.s

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2011-09-06-NoNewline.s

Move test to the X86 directory, note the PR number and only run MC once.

2011-10-31 17:23:09 +00:00

dg.exp

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intel-syntax-encoding.s

Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.

2012-01-24 21:43:36 +00:00

intel-syntax.s

Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]

2012-01-27 19:48:28 +00:00

padlock.s

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x86_64-avx-clmul-encoding.s

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x86_64-avx-encoding.s

Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.

2011-12-15 23:46:18 +00:00

x86_64-bmi-encoding.s

Add X86 SARX, SHRX, and SHLX instructions.

2011-10-23 22:18:24 +00:00

x86_64-encoding.s

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x86_64-fma3-encoding.s

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x86_64-fma4-encoding.s

Support for encoding all FMA4 instructions and tablegen patterns for all

2011-11-30 22:09:42 +00:00

x86_64-imm-widths.s

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x86_64-xop-encoding.s

XOP instructions and encoding tests.

2011-12-12 19:37:49 +00:00

x86_directives.s

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x86_errors.s

Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and

2011-10-27 17:40:41 +00:00

x86_operands.s

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x86-32-avx.s

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x86-32-coverage.s

Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and

2011-10-27 17:40:41 +00:00

x86-32-fma3.s

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x86-32.s

Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.

2011-10-07 05:35:38 +00:00

x86-64.s

X86: alias cqo to cqto.

2011-11-24 12:02:46 +00:00